參數(shù)資料
型號(hào)： SAA2003
廠商： NXP Semiconductors N.V.
元件分類(lèi)： Codec
英文描述： Stereo filter and codec
中文描述： 過(guò)濾器和立體聲編解碼器
文件頁(yè)數(shù)： 29/44頁(yè)
文件大?。?/td> 176K
代理商： SAA2003
May 1994
35
Philips Semiconductors
Preliminary specication
Stereo lter and codec
SAA2003
Timing characteristics FDIR and SYNCDAI; see Fig.26
tsH
SYNCDAI HIGH time
1280
ns
td1
internal clock delay time after
SYNCDAI LOW
0
ns
td2
external clock delay time after
SYNCDAI LOW
320
ns
td3
FDIR delay time before
SYNCDAI HIGH
280
ns
td4
external clock delay time
before SYNCDAI HIGH
320
ns
td5
internal clock delay time
before SYNCDAI HIGH
0
ns
Baseband data interface timing characteristics
MASTER MODE; SEE FIGS 17 AND 18
Tc
SCK cycle time
fs = 48 kHz
325.6
ns
tcH
SCK HIGH time
fs = 48 kHz
143
ns
tcL
SCK LOW time
fs = 48 kHz
143
ns
td1
FS256 HIGH delay time until
SCK transition
0
50
ns
th2
WS, SD1 and SD2 hold time
after FS256 HIGH
0
ns
td2
FS256 delay time until WS,
SD1 and SD2 valid
0
50
ns
tsu
SD1 input set-up time before
SCK HIGH
30
ns
th1
SD1 input hold time after SCK
HIGH
0
ns
SLAVE MODE; SEE FIG.19
Tc
SCK cycle time
fs = 48 kHz
325.6
651.2
ns
tcH
SCK HIGH time
fs = 48 kHz
116
ns
tcL
SCK LOW time
fs = 48 kHz
116
ns
tsu
WS and SD1 inputs set-up
time before SCK HIGH
30
ns
th1
WS and SD1 inputs hold time
after SCK HIGH
0
ns
th2
SD1 and SD2 outputs hold
time after SCK HIGH
66
ns
td
SCK delay time until SD1 and
SD2 outputs valid
223
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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