參數(shù)資料
型號(hào): SAA2003
廠商: NXP Semiconductors N.V.
元件分類: Codec
英文描述: Stereo filter and codec
中文描述: 過濾器和立體聲編解碼器
文件頁數(shù): 28/44頁
文件大小: 176K
代理商: SAA2003
May 1994
34
Philips Semiconductors
Preliminary specication
Stereo lter and codec
SAA2003
Drive processing interface timing; see Fig.23
tcy
SCK cycle time
1302
ns
tcH
SCK HIGH time
460
651
ns
tcL
SCK LOW time
460
651
ns
td1
SBWS and SBDA delay time
until SCK LOW
20
ns
td2
SCK delay time until SBWS
and SBDA valid
20
ns
tsu1
SBDA input set-up time before
SCK HIGH
235
ns
th1
SBDA input hold time after
SCK HIGH
30
ns
tsu2
set-up time from SCK HIGH
until SBEF valid
90
ns
th2
SBEF input hold time after
SCK HIGH
380
ns
Filtered data interface timing; see Fig.21
FDCL, FDWS, FDAI AND FDAO
f256
FS256 frequency
fs = 48 kHz
12.288
MHz
fs = 44.1 kHz
11.2896
MHz
fs = 32 kHz
8.192
MHz
Tc
FDCL cycle time
fs = 48 kHz
325.6
ns
tFH
FS256 HIGH time
fs = 48 kHz; note 2
35
ns
fs = 44.1 kHz; note 2
38
ns
fs = 32 kHz; note 2
75
ns
tFL
FS256 LOW time
fs = 48 kHz; note 2
35
ns
fs = 44.1 kHz; note 2
38
ns
fs = 32 kHz; note 2
35
ns
td1
FS256 delay time until FDCL
transition
0
50
ns
tcH
FDCL HIGH time
fs = 48 kHz
143
ns
tcL
FDCL LOW time
fs = 48 kHz
143
ns
th2
FDWS, FDAO and FSYNC
hold time after FS256 HIGH
0
ns
td2
FS256 HIGH delay time until
FDWS, FDAO and FSYNC
valid
0
50
ns
tsu
FDAI input set-up time before
FS256 HIGH
20
ns
th1
FDAI input hold time after
FS256 HIGH
30
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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