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參數(shù)資料
| 型號(hào)： | S6C0672 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER |
| 中文描述： | 6通道384位的TFT - LCD源驅(qū)動(dòng) |
| 文件頁(yè)數(shù)： | 7/19頁(yè) |
| 文件大?。?/td> | 206K |
| 代理商： | S6C0672 |
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6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
S6C0672
7
PIN DESCRIPTIONS
Symbol
Pin Name
Description
VDD1
VDD2
VSS1
VSS2
Y1 - Y384
D0<0:5>
- D5<0:5>
Logic power supply
Driver power supply
Logic ground
Driver ground
Driver outputs
2.7 - 3.6 V
7.0 - 13.0 V
Ground (0 V)
Ground (0 V)
The D/A converted 64 gray scale analog voltage is output.
The display data is input with a width of 36 bits,
gray-scale data (6 bits) by 6 dots (R,G,B) DX0: LSB, DX5: MSB
This pin controls the direction of shift register in cascade connection.
The shift direction of the shift registers is as follows.
SHL = H: DIO1 input, Y1
→
Y384, DIO2 output
SHL = L: DIO2 input, Y384
→
Y1, DIO1 output
Start pulse input / output SHL = H: Used as the start pulse input pin.
SHL = L: Used as the start pulse output pin.
Start pulse input / output SHL = H: Used as the start pulse output pin.
SHL = L: Used as the start pulse input pin.
DATPOL = L: Display data is not inverted
DATPOL = H: Display data is inverted
POL = H: The reference voltage for odd number outputs are VGMA1 –
VGMA5 and those for even number outputs are VGMA6 – VGMA10.
POL = L: The reference voltage for odd number outputs are VGMA6 –
VGMA10 and those for even number outputs are VGMA1 – VGMA5.
Refer to the shift register's shift clock input. the display data is loaded
to the data register at the rising edge of CLK2.
Latches the contents of the data register at rising edge and transfers
them to the D/A converter. Also, after CLK1 input, clears the internal
shift register contents. After 1 pulse input on start, operates normally.
CLK1 input timing refers to the "Relationships between CLK1 start
pulse (DIO1, DIO2) and blanking period" of the switching characteristic
waveform. Outputs the G/S data at falling edge.
Input the gamma corrected power supplies from external source.
VDD2 > VGMA1 > VGMA2 >
………
> VGMA9 > VGMA10 > VSS2
Keep gray-scale power supply unchanged during the gray-scale
voltage output.
TEST = L: Normal operation mode
TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 15k
)
Display data input
SHL
Shift direction control
input
DIO1
DIO2
DATPOL
Data inversion input
POL
Polarity input
CLK2
Shift clock input
CLK1
Latch input
VGMA1
–
VGMA10
Gamma corrected power
supplies
TEST
Test input
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