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參數(shù)資料
| 型號(hào)： | S6C0672 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER |
| 中文描述： | 6通道384位的TFT - LCD源驅(qū)動(dòng) |
| 文件頁(yè)數(shù)： | 17/19頁(yè) |
| 文件大小： | 206K |
| 代理商： | S6C0672 |
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6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
S6C0672
17
AC CHARACTERISTICS
Table 6. AC Characteristics (Ta = -20 to 75
°
C, VDD2 = 7 to 13 V, VDD1 = 2.7 to 3.6 V, VSS1 = VSS2 = 0 V)
Parameter
Clock pulse width
Clock pulse low period
Clock pulse high period
Data setup time
Data hold time
Start pulse setup time
Start pulse hold time
DATPOL-CLK2 setup
time
DATPOL-CLK2 hold time
Start pulse delay time
Symbol
PWCLK
PWCLK(L)
PWCLK(H)
tSETUP1
tHOLD1
tSETUP2
tHOLD2
Condition
-
-
-
(1)
(1)
(1)
(1)
Min.
15
5
5
3 / 5
0 / 2
3 / 5
0 / 2
Typ.
-
-
-
-
-
-
-
Max.
-
-
-
-
-
-
-
Unit
tSETUP4
(1)
3 / 5
-
-
tHOLD4
tPLH1
(1)
0 / 2
-
0
-
-
CL = 20 pF
12
ns
CLK1 setup time
tSETUP3
-
1
-
-
CLK2
period
Driver output delay time1
Driver output delay time2
CLK1 pulse high period
Data invalid period
Last data timing
CLK1-CLK2 time
POL-CLK1 time
tPHL1
tPHL2
PWCLK1
tINV
tLDT
tCLK1–CLK2
tPOL–CLK1
(2),(4)
(3),(4)
-
-
-
-
-
-
1
-
-
-
5
10
2
0.2
μ
s
DIO1 (2)
↑
→
CLK2
↑
-
CLK1
↑
→
CLK2
↑
POL
↑
or
↓
→
CLK1
↑
1
6
5
-
-
-
CLK2
period
ns
ns
NOTES:
1. Input condition (VIH = 0.7 VDD1, VIL = 0.3 VDD1 / VIH = 0.5 VDD1, VIL = 0.5 VDD1)
2. The value is specified when the drive voltage value reaches the target output voltage level of 90%
3. The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.
4. Yout Load Condition
VCOM = 0.5VDD2
10k
20k
20k
30pF
30pF
30pF
YOUT
Figure 5. Yout Load Condition
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