參數(shù)資料
型號: S5N8950
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: G.dmt ADSL Transceiver for CO and CPE
中文描述: G.dmt寬帶收發(fā)器對CO和CPE
文件頁數(shù): 6/19頁
文件大?。?/td> 203K
代理商: S5N8950
S5N8950
G.dmt ADSL Transceiver for CO and CPE
CONFIDENTIAL
Preliminary Information ( Rev 1.2 )
Interface
Type
Mnemonic
Type
Driver
Function
U_TX_ADDR[4:0]
U_TX_DATA[7:0]
U_TX_ENB
U_TX_SOC
U_TX_CLK
U_TX_CLAV
U_RX_ADDR[4:0]
U_RX_DATA[7:0]
U_RX_ENB
U_RX_SOC
U_RX_CLK
U_RX_CLAV
I
I
I
I
I
PHTICD
PHTICD
PHTICD
PHTICD
PHTICD
PHTOT4
PHTICD
PHTOT4
PHTICD
PHTOT4
PHTICD
PHTOT4
Utopia Tx Address
Utopia Tx Data
Utopia Tx Enable
Utopia Tx Start of Cell
Utopia Tx Clock. 25 MHz
Utopia Tx Cell Available
Utopia Rx Address[4:0]
Utopia Rx Data[7:0]
Utopia Rx Enable
Utopia Rx Start of Cell
Utopia Rx Clock. 25 MHz
Utopia Rx Cell Available
OZ
I
OZ
I
OZ
I
OZ
ATM
interface
S1_TX_DAV
S1_TX_CLK
S1_TX_DATA
S1_RX_DAV
S1_RX_CLK
S1_RX_DATA
S2_TX_DAV
S2_TX_CLK
S2_TX_DATA
S2_RX_DAV
S2_RX_CLK
S2_RX_DATA
O
O
I
O
O
O
O
O
I
O
O
O
PHOB4
PHOB4
PHTICD
PHOB4
PHOB4
PHOB4
PHOB4
PHOB4
PHTICD
PHOB4
PHOB4
PHOB4
Serial Tx data valid signal in the 1-st STM
Serial Tx clock in the 1-st STM
Serial Tx data in the 1-st STM
Serial Rx data valid signal in the 1-st STM
Serial Rx clock in the 1-st STM
Serial Rx data in the 1-st STM
Serial Tx data valid signal in the 2-nd STM
Serial Tx clock in the 2-nd STM
Serial Tx data in the 2-nd STM
Serial Rx data valid in the 2-nd STM
Serial Rx clock in the 2-nd STM
Serial Rx data in the 2-nd STM
STM
interface
H_SEL
H_ADDR[9:0]
H_DATA[7:0]
H_CSN
I
I
PHTICD
PHTICD
PHTBCDT6SM
PHTICD
Host type : [0]=Motorola / [1]= Intel
Host address bus
Host data bus
Chip selection
Motorola
Not used.
Intel
Read enable ( active low )
Motorola
[0]=write enable / [1]=read enable
Intel
Write Enable ( active low )
Motorola
Host CPU DTACK ( active low )
Intel
Host CPU Ready (active high )
Motorola
Interrupt IRQ ( active low )
Intel
Interrupt INT ( active high )
Host Wakeup
B
I
H_RDN
I
PHTICD
H_WRN
I
PHTICD
H_READY
OZ
PHTOT4
H_INT
O
PHOB4
H_WAKEUP
O
PHOB4
Host
Interface
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