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參數(shù)資料
| 型號(hào)： | S3P7559-AT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDIP64 |
| 封裝： | 0.750 INCH, SDIP-64 |
| 文件頁數(shù)： | 12/197頁 |
| 文件大?。?/td> | 1181K |
| 代理商： | S3P7559-AT |
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S3C7559/P7559
POWER-DOWN
8-1
8
POWER-DOWN
OVERVIEW
The S3C7559 microcontroller has two power-down modes to reduce power consumption: idle and stop. Idle
mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP instructions must
always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while peripherals
and the oscillation source continue to operate normally.
When
RESET occurs during normal operation or during a power-down mode, a reset operation is initiated and
the CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has
elapsed, normal CPU operation resumes.
In stop mode, main system clock oscillation is halted (assuming it is currently operating), and peripheral hard-
ware components are powered-down. The effect of stop mode on specific peripheral hardware components —
CPU, basic timer, serial I/O, timer/counters, and watch timer — and on external interrupt requests, is detailed in
Table 8-1.
Idle or stop modes are terminated either by a
RESET, or by an interrupt with the exception of INT0, which are
enabled by the corresponding interrupt enable flag, IEx. When power-down mode is terminated by
RESET input,
a normal reset operation is executed. Assuming that both the interrupt enable flag and the interrupt request flag
are set to "1", power-down mode is released immediately upon entering power-down mode.
When an interrupt is used to release power-down mode, the operation differs depending on the value of the
interrupt master enable flag (IME):
— If the IME flag = "0", if the power down mode release signal is generated, after releasing the power-down
mode, program execution starts immediately under the instruction to enter power down mode without
execution of interrupt service routine. The interrupt request flag remains set to logic one.
— If the IME flag = "1", if the power down mode release signal is generated, after releasing the power down
mode, two instructions following the instruction to enter power down mode are executed first and the interrupt
service routine is executed, finally program is resumed.
However, when the release signal is caused by INT2 or INTW, the operations is identical to the IME = “0”
condition because INT2 and INTW are a quasi-interrupt.
NOTE
Do not use stop mode if you are using an external clock source because Xin input must be restricted
internally to VSS to reduce current leakage
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