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參數(shù)資料
| 型號(hào)： | S3C72N5XX-QW |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, QFP-80 |
| 文件頁數(shù)： | 6/215頁 |
| 文件大?。?/td> | 1419K |
| 代理商： | S3C72N5XX-QW |
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S3C72N8/P72N8/C72N5/P72N5
POWER-DOWN
8-1
8
POWER-DOWN
OVERVIEW
The S3C72N8/C72N5 microcontroller has two power-down modes to reduce power consumption: idle and stop.
Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP instructions
must always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while
peripherals and the oscillation source continue to operate normally.
When RESET occurs during normal operation or during a power-down mode, a reset operation is initiated and the
CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has
elapsed, normal CPU operation resumes.
In main stop mode, main system clock oscillation is halted (assuming main clock is selected as system clock and
it is currently operating), and peripheral hardware components are powered-down. In sub stop mode, (assuming
sub clock is selected) sub system clock oscillation is halted by setting SCMOD.2 to “1”. The effect of stop mode
on specific peripheral hardware components — CPU, basic timer, timer/ counter 0, watch timer, and LCD
controller, serial I/O — and on external interrupt requests, is detailed in Table 8-1.
NOTE
Do not use stop mode if you are using an external clock source because X
IN input must be restricted
internally to V
SS to reduce current leakage.
Idle or main stop modes are terminated either by a RESET, or by an interrupt which is enabled by the
corresponding interrupt enable flag, IEx. When power-down mode is terminated by RESET, a normal reset
operation is executed. Assuming that both the interrupt enable flag and the interrupt request flag are set to "1",
power-down mode is released immediately upon entering power-down mode. Sub stop mode can be terminated
by RESET only.
When an interrupt is used to release power-down mode, the operation differs depending on the value of the
interrupt master enable flag (IME):
— If the IME flag = "0", program execution starts immediately after the instruction issuing a request to enter
power-down mode is executed. The interrupt request flag remains set to logical one.
— If the IME flag = "1", two instructions are executed after the power-down mode release and the vectored
interrupt is then initiated. However, when the release signal is caused by INT2 or INTW, the operation is
identical to the IME = "0" condition. Assuming that both interrupt enable flag and interrupt request flag are set
to "1", the release signal is generated when power-down mode is entered.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S3C72N8 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:single-chip CMOS microcontroller |
| S3C72P9 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:SINGLE-CHIP MICROCONTROLLER HAS BEEN DESIGNED FOR HIGH PERFORMANCE USING |
| S3C72Q5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4?BIT CMOS MICROCONTROLLER USERS MANUAL |
| S3C7324 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7324 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 |
| S3C7335 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7335 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 |
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