參數(shù)資料
型號： S3C1860XX-DK
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP20
封裝： 0.300 INCH, DIP-20
文件頁數(shù)： 29/95頁
文件大小： 339K
代理商： S3C1860XX-DK
S3C1840/C1850/C1860/P1860
INSTRUCTION SET
5-7
MOV
@HL+,#n
Binary Code:
0 1 1 0
d d d d
Description:
The 4-bit value specified by n (data) is moved to data memory addressed by registers H,L;
L register contents are incremented by one.
The contents of the source operand are not affected.
Operation:
M [(H,L)]
← #n, L ← L + 1
Flags:
SF : Set to one
SL : Unaffected
Example:
MOV
H,#0H
MOV
L,#7H
MOV
@HL+,#9H
; Move 9H to RAM address 07H and increment REG L value
by one, then REG L contains 8H
MOVZ @HL,A
Binary Code:
0 0 1 0
0 1 1 0
Description:
The contents of the accumulator are moved to the data memory addressed by registers
H,L;
accumulator contents are cleared to zero.
Operation:
M [(H,L)]
← (A), (A) ← 0
Flags:
SF : Set to one
SL : Unaffected
Example:
MOV
L,#3H
MOV
A,L
MOVZ
@HL,A
; Move 3H to indirect RAM and clear A to zero
MOV
L,A
; Move 0H to REG L
SETB
P2.(L)
; Set P2.0 to 1
XCH @HL,A
Binary Code:
0 0 0 0
0 0 1 1
Description:
This instruction exchanges the contents of the data memory addressed by registers H and
L with the accumulator contents.
Operation:
M [(H,L)]
(A)
Flags:
SF : Set to one
SL : Unaffected
Example:
MOV
H,#0H
MOV
L,#6H
CLR
A
; Clear A to zero
ADDS
A,#5H
; Add 5H to A
XCH
@HL,A
; Exchange 5H with contents of RAM address 06H
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