參數(shù)資料
型號(hào)： S29XS064R0PBHW010
廠商： SPANSION LLC
元件分類： PROM
英文描述： 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44
封裝： 7.50 X 5 MM, LEAD FREE, FBGA-44
文件頁(yè)數(shù)： 9/65頁(yè)
文件大?。?/td> 2116K
代理商： S29XS064R0PBHW010
July 22, 2011 S29VS_XS064R_00_06
S29VS/XS-R MirrorBit
Flash Family
17
Da ta
Sh e e t
(Adv a n ce
In f o r m ation)
The upper address is set to Zero or all Ones, for bottom or top boot respectively, during a Hardware Reset,
operate in ADM mode during the early phase of boot code execution where only a single address cycle would
be issued with the lower 16 bit of the address reaching the memory in AADM mode. The default high order
address bits will direct the early boot accesses to the 128 Kbytes at the boot end of the device. Note that in
AADM interface mode this effectively requires that one of the boot sectors is selected for any address overlay
mode because in the initial phase of AADM mode operation the host memory controller may only issue the
low order address thus limiting the early boot time address space to the 128 Kbytes at the boot end of the
device.
8.3
Default Access Mode
Upon power-up or hardware reset, the device defaults to the Asynchronous Access mode.
9.
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the device. Table 9.1 lists the device bus operations, the
inputs and control levels they require, and the resulting output. The following subsections describe each of
these operations in further detail.
Legend
L = Logic 0, H = Logic 1, X = Don’t Care.
Table 9.1 Device Bus Operations
Operation
CE#
OE#
WE#
Amax–16
A/DQ15–0
RESET#
CLK
AVD#
Standby (CE#)
H
X
High-Z
H
H/L
X
Hardware Reset
X
High-Z
L
X
Asynchronous Address Latch
- ADM mode (29VS064R only)
L
H
X
Addr In
H
X
Asynchronous Upper Address Latch
- AADM mode (29XS064R only)
L
H
X
Addr In
H
X
Asynchronous Lower Address Latch
- AADM mode (29XS064R only)
L
H
X
Addr In
H
X
Asynchronous Read
L
H
Addr In
I/O
H
L
Write
L
H
L
Addr In
I/O
H
H/L
Burst Read Operations
Latch Starting Burst Address by CLK
-ADM mode (29VS064R only)
L
H
Addr In
H
L
Latch Upper Starting Burst Address by CLK -AADM mode
(29XS064R only)
L
H
X
Addr In
H
L
Latch Lower Starting Burst Address by CLK -AADM mode
(29XS064R only)
L
H
X
Addr In
H
L
Advance Burst to next address with appropriate Data
presented on the Data Bus
LL
H
X
Burst
Data Out
HH
Terminate current Burst read cycle
H
X
H
X
High-Z
H
X
Terminate current Burst read cycle via RESET#
X
H
X
High-Z
L
X
Terminate current Burst read cycle and start new Burst
read cycle
L
H
X
I/O
H
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