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參數(shù)資料
| 型號： | S29XS064R0PBHW010 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封裝： | 7.50 X 5 MM, LEAD FREE, FBGA-44 |
| 文件頁數(shù)： | 15/65頁 |
| 文件大小： | 2116K |
| 代理商： | S29XS064R0PBHW010 |
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22
S29VS/XS-R MirrorBit
Flash Family
S29VS_XS064R_00_06 July 22, 2011
Data
Sheet
(Adv an ce
Inf o r m a t io n)
9.5
Configuration Register
The device uses a configuration register to set the various burst parameters: number of wait states, burst
read mode, burst length, RDY configuration, and synchronous mode active.
9.6
Handshaking Feature
The handshaking feature allows the host system to simply monitor the RDY signal from the device to
determine when the initial word of burst data is ready to be read. The host system should use the
configuration register to set the number of wait states for optimal burst mode operation. The initial word of
burst data is indicated by the rising edge of RDY after OE# goes low.
9.7
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while programming or erasing in one of the
other banks of memory. An erase operation may also be suspended to read from or program to another
location within the same bank (except the sector being erased). Figure 19.12, on page 62 shows how read
and write cycles may be initiated for simultaneous operation with zero latency. Refer to Table 16.1, CMOS
Compatible on page 52 for read-while-program and read-while-erase current specifications.
9.8
Writing Commands/Command Sequences
The device has inputs/outputs that accept both address and data information. To write a command or
command sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive
WE# and CE# to VIL, and OE# to VIH. when writing commands or data.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 14-17 indicates the
address space that each sector occupies. The device address space is divided into multiple banks. A “bank
address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address
bits required to uniquely select a sector.
Refer to Table 16.1, CMOS Compatible on page 52 for write mode current specifications. The AC
Characteristics on page 54 section contains timing specification tables and timing diagrams for write
operations.
9.9
Accelerated Program and Erase Operations
The device offers accelerated program and erase operation through the VPP function. VPP is primarily
intended to allow faster manufacturing throughput at the factory and not to be used in system operations.
If the system asserts VHH on this input, the device uses the higher voltage on the input to reduce the time
required for program and erase operations. Removing VHH from the VPP input, upon completion of the
embedded program or erase operation, returns the device to normal operation. Note that sectors must be
unlocked prior to raising VPP to VHH. Note that the VPP pin must not be at VHH for operations other than
accelerated programming, or device damage may result. In addition, the VPP pin must not be left floating or
unconnected; inconsistent behavior of the device may result.
When at VIL, VPP locks all sectors. VPP should be at VIH for all other conditions.
9.10
Write Buffer Programming Operation
Write Buffer Programming allows the system to write a maximum of 32 words in one programming
operation. This results in a faster effective word programming time than the standard “word” programming
algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address
in which programming will occur. At this point, the system writes the number of “word locations minus 1”
that will be loaded into the page buffer at the Sector Address in which programming will occur. This tells the
device how many write buffer addresses will be loaded with data and therefore when to expect the “Program
Buffer to Flash” confirm command. The number of locations to program cannot exceed the size of the write
buffer or the operation will abort. (NOTE: The number loaded = the number of locations to program minus 1.
For example, if the system will program 6 address locations, then 05h should be written to the device.)
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