參數(shù)資料
型號: S29NS128P
廠商: Spansion Inc.
英文描述: MirrorBit Flash Family
中文描述: MirrorBit閃存系列
文件頁數(shù): 77/86頁
文件大小: 2234K
代理商: S29NS128P
February 20, 2007 S29NS-P_00_A1
S29NS-P MirrorBit
TM
Flash Family
77
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
10.9
Erase and Programming Performance
Notes
1. Typical program and erase times assume the following conditions: 25
°
C, 1.8 V V
CC
, 10,000 cycles using checkerboard patterns.
2. Under worst case conditions of 90°C, V
CC
= 1.70 V, 100,000 cycles.
3. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
4. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 11.1,
Memory Array Commands on page 78
and
Table 11.2, Sector Protection Commands on page 80
for further information on command
definitions.
Table 10.11
Erase and Programming Performance
Parameter
Typ
(1)
Max
(2)
Unit
Comments
Sector Erase Time
64 Kword
V
CC
0.8
3.5
s
Excludes 00h
programming prior to
erasure
(3)
16 Kword
V
CC
0.15
2.0
64 Kword
V
PP
0.8
3.5
16 Kword
V
PP
0.15
2.0
Sector Erase Time
64 Kword
V
CC
0.90
5.00
Includes 00h
programming prior to
erasure
(3)
16 Kword
V
CC
0.45
1.85
64 Kword
V
PP
0.70
3.75
16 Kword
V
PP
0.35
1.40
Chip Erase Time
V
CC
77 (NS128P)
154 (NS256P)
306 (NS512P)
154 (NS128P)
308 (NS256P)
612 (NS512P)
s
Word Programming Time
V
CC
40
400
μs
Excludes system level
overhead
(4)
V
PP
24
240
Effective Word Programming Time
utilizing Program Write Buffer
V
CC
9.4
94
μs
V
PP
6
60
Total 32-Word Buffer Programming
Time
V
CC
300
3000
V
PP
192
1920
Chip Programming Time (using 32
word buffer)
V
CC
78.6 (NS128P)
157.3 (NS256P)
314.6 (NS512P)
157.3 (NS128P)
314.6 (NS256P)
629.2 (NS512P)
s
Excludes system level
overhead
(4)
V
PP
51 (NS128P)
101 (NS256P)
202 (NS512P)
102 (NS128P)
202 (NS256P)
404 (NS512P)
Erase Suspend/Erase Resume
Min
20
μs
Program Suspend/Program Resume
Min
20
μs
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