參數(shù)資料
型號(hào)： S29NS128P0SBJW003
廠商： SPANSION LLC
元件分類(lèi)： DRAM
英文描述： MirrorBit Flash Family
中文描述： 8M X 16 FLASH 1.8V PROM, 80 ns, PBGA64
封裝： 6.20 X 7.70 MM , LEAD FREE, TFBGA-64
文件頁(yè)數(shù)： 59/86頁(yè)
文件大?。?/td> 2234K
代理商： S29NS128P0SBJW003
February 20, 2007 S29NS-P_00_A1
S29NS-P MirrorBit
TM
Flash Family
59
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Table 7.1
contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the
sector.
7.7
Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control:
When WP# is at V
IL
, the highest two sectors are locked (device specific).
When
V
PP
is at V
IL
, all sectors are locked.
There are additional methods by which intended or accidental erasure of any sectors can be prevented via
hardware means. The following subsections describes these methods:
WP# Method
The Write Protect feature provides a hardware method of protecting the highest two sectors (NS256P and
NS128P). This function is provided by the WP# pin and overrides the previously discussed Sector Protection/
Unprotection method.
If the system asserts V
IL
on the WP# pin, the device disables program and erase functions in the highest two
sectors (NS256P and NS128P) as well as Secured Silicon Area.
If the system asserts V
IH
on the WP# pin, the device reverts to whether the boot sectors were last set to be
protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether
they were last protected or unprotected.
Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may
result.
The WP# pin must be held stable during a command sequence execution
V
PP
Method
This method is similar to above, except it protects all sectors (including the Secured Silicon Area). Once V
PP
input is set to V
IL
, all program and erase functions are disabled and hence all sectors are protected.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This protects data during V
CC
power up and power down.
The command register and all internal program/erase circuits are disabled, and the device resets to reading
array data. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control inputs to prevent unintentional writes when V
CC
is greater than V
LKO
.
Write Pulse
Glitch Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Power-Up Write Inhibit
If WE# = CE# = RESET# = V
IL
and OE# = V
IH
during power up, the device does not accept commands on the
rising edge of WE#. The internal state machine is automatically reset to the read mode on power up.
相關(guān)PDF資料
PDF描述
S29NS128PABBJW000 MirrorBit Flash Family
S29NS128PABBJW003 MirrorBit Flash Family
S29NS256P MirrorBit Flash Family
S29NS256P0PBJW000 MirrorBit Flash Family
S29NS256P0PBJW003 MirrorBit Flash Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29NS128PABBJW000 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:MirrorBit Flash Family
S29NS128PABBJW003 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:MirrorBit Flash Family
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S29NS256N0PBJW000 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS256N0PBJW002 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
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