參數(shù)資料
型號: S29NS128P0SBJW003
廠商: SPANSION LLC
元件分類: DRAM
英文描述: MirrorBit Flash Family
中文描述: 8M X 16 FLASH 1.8V PROM, 80 ns, PBGA64
封裝: 6.20 X 7.70 MM , LEAD FREE, TFBGA-64
文件頁數(shù): 46/86頁
文件大小: 2234K
代理商: S29NS128P0SBJW003
46
S29NS-P MirrorBit
TM
Flash Family
S29NS-P_00_A1 February 20, 2007
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
6.5.9
Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The following
subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm
is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last
word being programmed in the write-buffer-page during Write Buffer Programming. Reading Data# Polling
status on any word other than the last word to be programmed in the write-buffer-page returns false status
information. Similarly, attempting to program
1
over a
0
does not return valid Date# information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. The system must
provide the program address to read valid status information on DQ7. If a program address falls within a
protected sector, Data# polling on DQ7 is active for approximately t
PSP
, then that bank returns to the read
mode.
During the Embedded Erase Algorithm, Data# polling produces a
0
on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a
1
on DQ7.
The system must provide an address within any of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately t
ASP
, then the bank returns to the read mode. If not all selected sectors are
protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors
that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may
not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously
with DQ6-DQ1 while Output Enable (OE#) is asserted low. That is, the device may change from providing
status information to valid data on DQ7. Even if the device has completed the program or erase operation and
DQ7 has valid data, the data outputs on DQ6-DQ1 may be still invalid. Valid data on DQ7-D01 appears on
successive read cycles.
See the following for more information:
Table 6.27
,
Write Operation Status
, shows the outputs for Data#
Polling on DQ7.
Table 6.5
,
Write Operation Status Flowchart
, shows the Data# Polling algorithm; and
Figure 10.15
,
Data# Polling Timings (During Embedded Algorithm)
, shows the Data# Polling timing diagram.
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