參數(shù)資料
型號(hào): S29JL032J70TFI213
廠商: SPANSION LLC
元件分類: PROM
英文描述: 2M X 16 FLASH 3V PROM, 70 ns, PDSO48
封裝: LEAD FREE, MO-142(D)DD, TSOP-48
文件頁(yè)數(shù): 58/63頁(yè)
文件大?。?/td> 1618K
代理商: S29JL032J70TFI213
August 24, 2011 S29JL032J_00_05
S29JL032J
61
Data
Sheet
21. Revision History
Section
Description
Revision 01 (January 27, 2010)
Initial release.
Revision 02 (June 15, 2010)
Global
Changed all references to typical Sector Erase time from 0.4 sec to 0.5 sec.
Changed all references to “Secured Silicon Sector” to “Secured Silicon Region”.
Corrected spelling and grammatical errors.
Product Selector Guide
Corrected Standard Voltage Range of 70 ns option from 3.0-3.6V to 2.7-3.6V.
Connection Diagrams
Added 48-ball FBGA connection diagram.
Pin Description
Changes “21 Addresses” to “21 Address Pins”.
Added clarification that CE#, OE#, WE#, BYTE#, and RY/BY# are Active Low.
Ordering Information
Added FBGA ordering option.
Added Low-halogen, Pb-free ordering option.
Added valid combinations for FBGA.
Word/Byte Configuration
Added clarification that BYTE# must be connected to either the system VCC or ground.
Secured Silicon Region
Added clarification that D7 is the Secured Silicon Factory Indicator Bit.
In Figure Secured Silicon Sector Protect Verify, corrected “Write reset command” to “Secured
Silicon Region exit command”.
Command Definitions
Corrected “Writing specific addresses and data commands or sequences” to “Writing specific
addresses and data sequences”.
Absolute Maximum Ratings
Corrected “A9, OE#, and RESET#” to “A9 and RESET#”.
DC Characteristics
Removed OE# from ILIT parameter description.
Removed OE# = 12.5V from ILIT test conditions.
Added 1 MHz to ICC6 and ICC7 test conditions.
Removed Note 1 from ICC6 and ICC7.
Test Conditions
Update Figure “Test Setup” to reflect correct test setup.
Added Note 1 to clarify that input rise and fall times are 0-100%.
Erase and Programming Performance
Changed Chip Erase typical time from 28 sec to 39 sec.
Removed Note 5.
Physical Dimensions
Added VBK048 package outline drawing.
Revision 03 (August 25, 2010)
Global
Updated the data sheet designation from Advanced Information to Preliminary.
Corrected spelling, capitalization, and grammatical errors.
Simultaneous Read/Write Operations
with Zero Latency
Clarified that JL032J can be configured as either a top or bottom boot sector device, not both.
Ordering Information
Corrected typo in valid combinations table from “…, 41, 41” to “…, 41, 42”.
Clarified that Note 1 applies to the Packing Type column.
RESET#: Hardware Reset Pin
Changed “Refer to AC Characteristics on page 48” to “Refer to Hardware Reset (RESET#) on page
49”.
Secured Silicon Region
Clarified the Secured Silicon Indicator Bit data based on factory and customer lock status.
Removed forward looking statements regarding factory locking features as they are supported in
this device.
Common Flash Memory Interface (CFI)
Clarified that once in the CFI query mode, the system must write the reset command to return to
reading array data.
Erase Suspend/Erase Resume
Commands
Added clarification that “It is not recommended to program the Secured Silicon Region after an
erase suspend, as proper device functionality cannot be guaranteed.”
Erase and Programming Performance
Added Note 5 regarding minimum program and erase cycle endurance.
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