參數(shù)資料
型號： S29GL256M10TAIR10
廠商： SPANSION LLC
元件分類： DRAM
英文描述： 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology
中文描述： 16M X 16 FLASH 3V PROM, 100 ns, PDSO56
封裝： MO-142EC, TSOP-56
文件頁數(shù)： 117/160頁
文件大?。?/td> 2142K
代理商： S29GL256M10TAIR10
April 30, 2004 S29GLxxxM_00A5
S29GLxxxM MirrorBit
TM
Flash Family
117
P r e l i m i n a r y
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. The system may use either OE# or CE#
to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 μs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 μs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table
33
shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit
algorithm. Figure 20 in the “AC Characteristics” section shows the toggle bit tim-
ing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical
form. See also the subsection on DQ2: Toggle Bit II.
相關PDF資料
PDF描述
S29GL256M10TAIR12 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology
S29GL256M10TAIR13 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology
S29GL256M10TAIR20 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology
S29GL256M10TAIR22 MOSFET, Switching; VDSS (V): 200; ID (A): 0.5; Pch : -; RDS (ON) typ. (ohm) @10V: 1.6; RDS (ON) typ. (ohm) @4V[4.5V]: 1.9; RDS (ON) typ. (ohm) @2.5V: -; Ciss (pF) typ: 120; toff (µs) typ: -; Package: TSSOP-8
S29GL256M10TAIR23 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology
相關代理商/技術參數(shù)
參數(shù)描述
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S29GL256M11FAIR12 制造商:Spansion 功能描述:256M (32MX8/16MX16) 3V REG, MIRRORBIT, FBGA64 IND - Trays
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S29GL256M11FAIR20 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 256M-Bit 32M x 8/16M x 16 110ns 64-Pin Fortified BGA Tray
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