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| 型號(hào)： | S29GL128P11FFIR10 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology |
| 中文描述： | 128M X 1 FLASH 3V PROM, 110 ns, PBGA64 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-64 |
| 文件頁(yè)數(shù)： | 75/77頁(yè) |
| 文件大?。?/td> | 2121K |
| 代理商： | S29GL128P11FFIR10 |
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November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit
Flash Family
75
D a t a
S h e e t
( P r e l i m i n a r y )
13. Advance Information on S29GL-R 65 nm MirrorBit Hardware
Reset (RESET#) and Power-up Sequence
Note
CE#, OE# and WE# must be at logic high during Reset Time.
Figure 13.1
Reset Timings
Note
The sum of t
RP
and t
RH
must be equal to or greater than t
RPH
.
Notes
1. V
IO
< V
CC
+ 200 mV.
2. V
IO
and V
CC
ramp must be in sync during power-up. If RESET# is not stable for 500 μs, the following conditions may occur: the device
does not permit any read and write operations, valid read operations return FFh, and a hardware reset is required.
3. Maximum V
CC
power up current is 20 mA (RESET# =V
IL
).
Figure 13.2
Power-On Reset Timings
Note
The sum of t
RP
and t
RH
must be equal to or greater than t
RPH
.
Table 13.1
Hardware Reset (RESET#)
Parameter
Description
Limit
Time
Unit
t
RPH
RESET# Low to CE# Low
Min
35
μs
t
RP
RESET# Pulse Width
Min
200
ns
t
RH
Time between RESET# (high) and CE# (low)
Min
200
ns
Table 13.2
Power-Up Sequence Timings
Parameter
Description
Limit
Time
Unit
t
VCS
V
CC
Setup Time to first access
Min
300
μs
t
VIOS
V
IO
Setup Time to first access
Min
300
μs
t
RPH
RESET# Low to CE# Low
Min
35
μs
t
RP
RESET# Pulse Width
Min
200
ns
t
RH
Time between RESET# (high) and CE# (low)
Min
200
ns
t
RPH
CE#
RESET#
t
RP
t
RH
CE#
V
CC
V
IO
RESET#
t
VIOS
t
VCS
t
RP
t
RH
t
RPH
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