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| 型號： | S29GL128P11FFIR10 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology |
| 中文描述： | 128M X 1 FLASH 3V PROM, 110 ns, PBGA64 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-64 |
| 文件頁數(shù)： | 56/77頁 |
| 文件大小： | 2121K |
| 代理商： | S29GL128P11FFIR10 |
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56
S29GL-P MirrorBit
Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a
S h e e t
( P r e l i m i n a r y )
11.7
AC Characteristics
11.7.1
S29GL-P Read-Only Operations
Notes
1. CE#, OE# = V
IL
2. OE# = V
IL
3. Not 100% tested.
4. See
Figure 11.3
and
Table 11.1
for test specifications.
5. Unless otherwise indicated, AC specifications for 110 ns speed options are tested with V
IO
= V
CC
= 2.7 V. AC specifications for 110 ns speed options are tested
with V
IO
= 1.8 V and V
CC
= 3.0 V.
Table 11.3
S29GL-P Read-Only Operations
Parameter
Description
(Notes)
Test Setup
Speed Options
JEDEC
Std.
90
100
110
120
130
Unit
t
AVAV
t
RC
Read Cycle Time
V
IO
= V
CC
= 2.7 V
V
IO
= 1.65 V to V
CC
,
V
CC
= 3 V
V
IO
= V
CC
= 3.0 V
V
IO
= V
CC
= 2.7 V
V
IO
= 1.65 V to V
CC
,
V
CC
= 3 V
V
IO
= V
CC
= 3.0 V
V
IO
= V
CC
= 2.7 V
V
IO
= 1.65 V to V
CC
,
V
CC
= 3 V
V
IO
= V
CC
= 3.0 V
Min
–
100
110
120
–
ns
–
–
110
120
130
90
100
110
–
–
t
AVQV
t
ACC
Address to Output Delay
(1)
Max
–
100
110
120
–
ns
–
–
110
120
130
90
100
110
–
–
t
ELQV
t
CE
Chip Enable to Output Delay
(2)
Max
–
100
110
120
–
ns
–
–
110
120
130
90
100
110
–
–
t
PACC
t
OE
t
DF
t
DF
Page Access Time
Max
25
ns
t
GLQV
t
EHQZ
t
GHQZ
Output Enable to Output Delay
Max
25
ns
Chip Enable to Output High Z
(3)
Max
20
ns
Output Enable to Output High Z
(3)
Max
20
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold Time
(3)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
CEH
Chip Enable Hold Time
Read
Min
35
ns
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