- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄192297 > S29GL032M10FAIR63 (Spansion Inc.) MirrorBit Flash Family PDF資料下載
參數(shù)資料
| 型號： | S29GL032M10FAIR63 |
| 廠商： | Spansion Inc. |
| 英文描述： | MirrorBit Flash Family |
| 中文描述： | MirrorBit閃存系列 |
| 文件頁數(shù)： | 85/159頁 |
| 文件大?。?/td> | 5216K |
| 代理商： | S29GL032M10FAIR63 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁當前第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
31
Da tash eet
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two functions provided
by the WP#/ACC or ACC pin, depending on model number. This function is primarily intended to allow faster man-
ufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode,
temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce the time
required for program operations. The system would use a two-cycle program command sequence as required by
the Unlock Bypass mode. Removing VHH from the WP#/ACC or ACC pin, depending on model number, returns the
device to normal operation. Note that the WP#/ACC or ACC pin must not be at VHH for operations other than ac-
celerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is
at VIH.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can
then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0.
Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” on page 79 and “Autoselect Com-
mand Sequence” on page 104 sections for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of
the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO ± 0.3 V. (Note
that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO ±
0.3 V, the device is in the standby mode, but the standby current is greater. The device requires standard access
time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is
completed.
Refer to “DC Characteristics” on page 122 for the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this
mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#,
and OE# control signals. Standard address access timings provide new data when addresses are changed. While
in sleep mode, output data is latched and always available to the system. Refer to “DC Characteristics” on
page 122 for the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin
is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all
output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets
the internal state machine to reading array data. The operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws
CMOS standby current (ICC5). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the Flash memory.
Refer to “AC Characteristics” on page 124 for RESET# parameters and to Figure 15, on page 127 for the timing
diagram.
相關PDF資料 |
PDF描述 |
|---|---|
| S29GL032M10FBCR32 | MirrorBit Flash Family |
| S29GL032M10FFIR50 | CAP 330UF 10V 20% COND-POLYMER SMD-7343-43 LOWESR-280 T&R |
| S29GL032M10FFIR52 | MirrorBit Flash Family |
| S29GL032M10FFIR53 | MirrorBit Flash Family |
| S29GL032M10FFIR60 | MirrorBit Flash Family |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S29GL032M10FBCR00 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology |
| S29GL032M10FBCR02 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10FBCR03 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10FBCR10 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29GL032M10FBCR12 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
發(fā)布緊急采購，3分鐘左右您將得到回復。