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參數(shù)資料
| 型號(hào)： | S29GL032M10FAIR63 |
| 廠商： | Spansion Inc. |
| 英文描述： | MirrorBit Flash Family |
| 中文描述： | MirrorBit閃存系列 |
| 文件頁數(shù)： | 84/159頁 |
| 文件大?。?/td> | 5216K |
| 代理商： | S29GL032M10FAIR63 |
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S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
Data s he et
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE#
pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active
and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input
for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control
and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at
VIH.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on
the device address inputs produce valid data on the device data outputs. The device remains enabled for read
access until the command register contents are altered.
See ““Reading Array Data” on page 103” for more information. Refer to “AC Characteristics” on page 124 for tim-
ing specifications and the timing diagram. Refer to “DC Characteristics” on page 122 for the active current
specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation.
This mode provides faster read access speed for random locations within a page. The page size of the device is 4
words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2. Address bits A1–A0 in
word mode (A1–A-1 in byte mode) determine the specific word within a page. This is an asynchronous operation;
the microprocessor supplies the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the lo-
cations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and
reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode accesses are obtained by keep-
ing the “read-page addresses” constant and changing the “intra-read page” addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors
of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock
Bypass mode, only two write cycles are required to program a word, instead of four. The “Word Program Com-
mand Sequence” on page 104” section contains details on programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 6 on page 32 and Table 17
on page 68 indicates the address space that each sector occupies.
Refer to “DC Characteristics” on page 122 for the active current specification for the write mode. The “AC Char-
acteristics” on page 124 section contains timing specification tables and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming op-
eration. This results in faster effective programming time than the standard programming algorithms. See ““Write
Buffer Programming” on page 105” for more information.
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