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參數(shù)資料
| 型號： | S2202 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual GigaBit Ethernet Transceiver(帶鎖相環(huán)時鐘合成器的雙千兆位以太網(wǎng)收發(fā)器) |
| 中文描述： | 雙千兆以太網(wǎng)收發(fā)器（帶鎖相環(huán)時鐘合成器的雙千兆位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 231K |
| 代理商： | S2202 |
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8
DUAL GIGABIT ETHERNET DEVICE
S2202
October 9, 2000 / Revision C
Data Output
Data is output on the DOUT[0:9] outputs. The
COM_DET signal is used to indicate the reception of a
valid K28.5 character.
The S2202 TTL outputs are optimized to drive 65
line impedances. Internal source matching provides
good performance on unterminated lines of reason-
able length.
Parallel Output Clock Rate
Two output clock modes are supported, as shown in
Table 5. When CMODE is High, a complementary
TTL clock at the data rate is provided on the RBC1/
0x outputs. Data should be clocked on the rising
edge of RBC1x. When CMODE is Low, a comple-
mentary TTL clock at half the data rate is provided.
Data should be latched on the rising edge of RBC1x
and the rising edge of RBC0x.
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D
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2
1
Table 5. Output Clock Mode
In Gigabit Ethernet applications, multiple consecu-
tive K28.5 characters cannot be generated. How-
ever, for serial backplane applications this can
occur. The S2202 must be able to operate properly
when multiple K28.5 characters are received. After
the first K28.5 is detected and aligned, the RBC1/0x
clock will operate without glitches or loss of cycles.
Receiver Output Clocking
The S2202 parallel output clock source is deter-
mined by the TMODE selection. When REFCLK
clocking is selected (TMODE = Low), the parallel
output clocks (RCxP/N) are sourced from the TCLKA
input. When TCLK clocking is selected (External
Clocking Mode), the parallel output clocks are de-
rived from the recovered clock from each channel.
Table 5A describes the receiver output clocking op-
tions available.
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B
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C
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Table 5A. S2202 Data Clocking
When TCLKA is the output clock source, REFCLK
and TCLKA must equal the parallel word rate
(CLKSEL = Low). Additionally, the recovered clocks
and the clock input on TCLKA must be frequency
locked in order to avoid overflow/underflow of the
internal FIFOs. The propagation delay between
TCLKA and DOUTx, listed in Table 21, shows that
the phase delay between TCLKA and the RCxP/N
outputs may vary more than a bit time based on
process variation.
The recommended clocking configuration for exter-
nal clocking mode (REFCLK input clocking) is shown
in Figure 7. TCLKA is sourced from TCLKO, which is
frequency locked to the Reference clock input.
REFCLK
TCLKO
SerDes
TCLKA
REF
OSCILLATOR
Controller/MAC
ASIC/FPGA
PLL
Parallel Data
RCxP/N
2
Recovered
Clock
Figure 7. External Receiver Clocking
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| S22MD2 | Photothyristor Coupler |
| S22MD3 | MICA RoHS Compliant: No |
| S22MD1V | Silver Mica Capacitor; Capacitance:2400pF; Capacitance Tolerance:+/- 5%; Series:CM06; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:8.7mm; Leaded Process Compatible:No RoHS Compliant: No |
| S2370 | HIGH SPEED, HIGH CURRENT SWITCHING APPLICATIONS. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S-2202A | 制造商:Honeywell Sensing and Control 功能描述: |
| S-2202E | 制造商:Honeywell Sensing and Control 功能描述: |
| S2202TB | 制造商:AppliedMicro 功能描述: |
| S2202TRI | 制造商:AppliedMicro 功能描述: |
| S2204TB | 制造商:AppliedMicro 功能描述:QUAD GIGABIT ETHERNET DEVICE |
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