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參數(shù)資料
| 型號(hào)： | S2202 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual GigaBit Ethernet Transceiver(帶鎖相環(huán)時(shí)鐘合成器的雙千兆位以太網(wǎng)收發(fā)器) |
| 中文描述： | 雙千兆以太網(wǎng)收發(fā)器（帶鎖相環(huán)時(shí)鐘合成器的雙千兆位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 231K |
| 代理商： | S2202 |
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6
DUAL GIGABIT ETHERNET DEVICE
S2202
October 9, 2000 / Revision C
Table 2. Data to 8B/10B Alphabetic Representation
Table 3. Operating Rates
E
T
A
R
L
E
S
K
L
C
K
c
L
n
C
e
u
F
E
q
e
R
r
y
F
l
e
t
u
p
S
t
e
R
u
O
O
n
K
e
L
u
C
q
T
e
r
y
c
F
0
0
z
H
M
5
2
1
z
H
M
0
5
2
1
z
H
M
5
2
1
0
1
z
H
M
5
6
z
H
M
0
5
2
1
z
H
M
5
2
1
1
0
z
H
M
5
6
z
H
M
5
2
6
z
H
M
5
6
1
1
z
H
M
5
2
3
z
H
M
5
2
6
z
H
M
5
6
.
Figure 5. DIN Data Clocking with TBC
REFCLK
S2202
125 MHz or 62.5 MHz
TBCx
DINx[0:9]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
e
B
a
D
]
U
O
D
r
]
N
I
D
0 1 2 3 4 5 6 7 8 9
c
m
u
n
n
a
h
p
o
e
B
s
0
1
B
e
e
R
8
a b
c
d e
i
f
g h
j
Table 2 identifies the mapping of the 8B/10B charac-
ters to the data inputs of the S2202. The S2202 will
serialize the parallel data for each channel and will
transmit bit “a” or DIN[0] first.
Frequency Synthesizer (PLL)
The S2202 synthesizes a serial transmit clock from
the reference signal. Upon startup, the S2202 will
obtain phase and frequency lock within 2500 bit
times after the start of receiving reference clock in-
puts. Reliable locking of the transmit PLL is assured,
but a lock-detect output is NOT provided.
Reference Clock Input
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within 200 ppm of each other to ensure
that the clock recovery units can lock to the serial
data. Gigabit Ethernet applications may require
tighter tolerances.
The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL=1. In both cases the fre-
quency of the parallel word rate output, TCLKO, is
constant at 1/10 the serial data rate. See Table 3.
Serial Data Outputs
The S2202 provides LVPECL level serial outputs.
The serial outputs do not require output pulldown
resistors. Outputs are designed to perform optimally
when AC-coupled.
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable
delivery of data and TBC to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET signal. TCLKO will oper-
Figure 6. GE DIN Clocking with REFCLK
REFCLK
S2202
TBCx
DINx[0:9]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
125 MHz
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| S22MD3 | MICA RoHS Compliant: No |
| S22MD1V | Silver Mica Capacitor; Capacitance:2400pF; Capacitance Tolerance:+/- 5%; Series:CM06; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:8.7mm; Leaded Process Compatible:No RoHS Compliant: No |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S-2202A | 制造商:Honeywell Sensing and Control 功能描述: |
| S-2202E | 制造商:Honeywell Sensing and Control 功能描述: |
| S2202TB | 制造商:AppliedMicro 功能描述: |
| S2202TRI | 制造商:AppliedMicro 功能描述: |
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