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參數(shù)資料
| 型號： | S1M8657X01-E0T0 |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, LQFP-48 |
| 文件頁數(shù)： | 16/34頁 |
| 文件大?。?/td> | 281K |
| 代理商： | S1M8657X01-E0T0 |
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TX IF/BBA WITH AGC
S1M8657
23
Table 5. Enhanced-Mode Input Range Selection
GPADCV[5:2]
Vin(Mid)
Input Range
LSB mV/Step
Zin
0000
1.0V
1V
4
∞
0001
2.0V
1V
4
∞
0010
1.5V
2V
8
∞
0011
1.5V
2V
8
∞
0100
0.75V
0.5V
2
∞
0101
1.5V
2V
8
∞
0110
1.5V
2V
8
∞
0111
1.5V
2V
8
∞
1000
0.5V
1V
4
∞
1001
1.0V
2V
8
∞
1010
1.25V
0.5V
2
∞
1011
1.5V
1V
4
∞
1100
2.0V
2V
8
∞
1101
1.5V
0.5V
2
∞
1110
1.75V
0.5V
2
∞
1111
2.0V
0.5V
2
∞
GP-ADC Enhanced Mode inputs are shown in Table 5. The IC input impedance is always kept high to reduce the
loading effect of the input impedance. However, if the external input divider impedance is very large, the
parasitic capacitor cannot charge or discharge quickly enough, generating a high speed conversion error.
Therefore, it is best to use a low resistance at the input terminal. The LSB step is the difference between the
input voltages that generate two codes, respectively. This is shown in Table 5. The GP-ADC needs the clock for
conversion. This clock self-divides and uses TCXO and influences the conversion time. Although a 412kHz clock
was used in S1M8653B, this IC can select from clock speeds between 308kHz – 1.23 MHz, as shown in Table 6,
according to the contents in SPI register GPADC_MODE[6:7]. The recommended clock speed is between
410kHz – 615kHz.
Table 6. GP-ADC Clock Divide Ratio
GPADC_MODE[7:6]
Clock Divide Ratio
System Clock(TCXO = 19.68MHz)
00
16
1.23MHz
01
32
615kHz
10
48
410kHz
11
64
308kHz
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| S1M8657X01-F0T0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:TX IF/BBA WITH AGC |
| S1M8660A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:RX IF / BBA WITH GPS |
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| S1M8662A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CDMA/PCS/GPS Triple Mode IF/ baseband IC |
| S1M8662AX01-F0T0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CDMA/PCS/GPS Triple Mode IF/ baseband IC |
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