參數(shù)資料
型號(hào)： S1M8657X01-E0T0
元件分類： 無(wú)繩電話/電話
英文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48
封裝： 7 X 7 MM, LQFP-48
文件頁(yè)數(shù)： 11/34頁(yè)
文件大?。?/td> 281K
代理商： S1M8657X01-E0T0
TX IF/BBA WITH AGC
S1M8657
19
The A and B-Counter divide ratios can be changed by programming the PLLNO and PLLN1 among the SPI
registers. They pass through the VCO internal output, TXVCO_OUT, and are input to the prescaler, and the
prescaler outputs are input to A and B-counters. If the B-Counter is not "0", the Prescaler divides by P+1(division
ratio of 9 or 17 ); if B-Counter is "0", the Prescaler divides by P(division ratio 8 or 16). If A-Counter becomes "0",
N-Counter is reset. If A-Counter output becomes fv, this becomes the comparison input for the PD (phase
comparator). R-Counter can be changed by programming PLLR0 and PLLR1 of the SPI registers. As a 10-bit
divider, R-Counter divides TCXO, which is then used as the reference input for the PD.
9- bit A-counter
PLLN1[4:0]
PLLN0[7:4]
PLLN0[3:0]
4-bit B-counter
MSB
LSB
Figure 8. Map of N Counter
PLLR0[7:0]
PLLR1[1:0]
MSB
LSB
Figure 9. Map of R Counter
The N-counter divide ratio (N) changes according to the prescaler value and is determined by the following
equation.
N = P
× A + B, where A ≤ 512, 0 ≤ B ≤ (P-1), and B < A.
The prescaler can use PLLN1[7] to select from either 8/9 or 16/17, the reference value being 16/17. If this bit
becomes "0", 8/9 is chosen as the prescaler divide ratio. N-Counter, composed of the 9-BIT A-Counter and 4BIT
B-Counter, lowers the VCO frequency and sends it to the PD.
PLL equation : N-Counter divide ratio N = fVCO/fPD
A-Counter divide ratio A = Int(N/P), A
≤ 512.
The value of A written into PLLN1 and PLLN0 as shown in Figure 8 is a binary value for A-1. For example, the
reference values, PLLN1[4:0]=00000 and PLLN0[7:4]=1100, are decimal, 12, and A is for 13.
The B-counter can be programmed with PLLN0[3:0].
B = N - P
× A, 0 ≤ B ≤ 15, P=16
The reference value for A and B-Counter (A=13, B=4) makes the VCO oscillating frequency equal to 260.76 MHz
when TCXO is at 19.68MHz, and PD phase comparison frequency becomes 1.23MHz.
The 10-bit R-counter can be programmed using the SPI registers, PLLR0 and PLLR1.
The R-Counter makes the f
R input signal for PD based on the TCXO reference signal.
R-Counter divide ratio R = fREF/fPD
The R-counter value set based on PLLR0 and PLLR1 is for R-1; for example, when PLLR0 = 00001111 and
PLLR1=00, decimal value is 15, but it is R-1, real value R is 16.
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