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參數(shù)資料
| 型號(hào)： | S1D15E06D03B000 |
| 廠商： | 愛普生（中國(guó)）有限公司 |
| 英文描述： | Direct RAM data display by display data RAM |
| 中文描述： | RAM數(shù)據(jù)顯示直接由顯示數(shù)據(jù)RAM |
| 文件頁(yè)數(shù)： | 34/74頁(yè) |
| 文件大?。?/td> | 490K |
| 代理商： | S1D15E06D03B000 |
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S1D15E06 Series
Rev. 2.1
EPSON
31
(10) Display Data Read
This command allows the 8-bit data to be read from the address specified by the display data RAM. After reading,
column address or page address is automatically incremented +1 by the Display Data Input Direction select command.
This enables the MPU to read multiple word data continuously.
It should be noted that one dummy reading is essential immediately after the column address or page address has been
set. For details, see the description of “6.1.5 Access to display data RAM and internal register” in the Function
Description. When the serial interface is used, display data cannot be read.
E
R/W
WR
0
1
A0
0
1
RD
1
0
D7
0
D6
0
D5
0
D4
1
Read Data
D3
1
D2
1
D1
0
D0
0
(11) Display Data Input Direction Select
This command sets the direction where the display RAM address number is automatically incremented. For details,
see the description of “6.2.3 Column address circuit” in the Function Description.
E
R/W
WR
0
A0
0
RD
1
D7
1
D6
0
D5
0
D4
0
D3
0
D2
1
D1
0
D0
0
1
Direction
Column
Page
(12) Column Address Set Direction
This command can reverse the relationship between the display RAM data column address and segment driver output
shown in Fig. 6.5 and 6.6. So you can reverse the sequence of segment driver output pins using this command. When
the display data is written or read, the column address is incremented by (+1) according to the column address given
in Fig. 6.4 and 6.5. For details, see the description of “6.2.3 Column address circuit” in the Function Description.
(13) n-line Inversion Drive Register Set
This command sets the liquid crystal alternating drive reverse line count in the register to start line reverse driving
operation. The line count to be set is 4 to 128 (32 states for each 4 lines. For details, see the description of “6.4 Display
timing generation circuit” in the Function Description.
E
R/W
WR
0
A0
0
RD
1
D7
1
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
1
Setting
Normal
Reverse
E
R/W
WR
0
0
A0
0
1
RD
1
1
D7
0
*
D6
0
*
D5
1
*
D4
1
P4
D3
0
P3
D2
1
P2
D1
1
P1
D0
0
P0
Reverse line count
Command
Reverse line count
*: denote invalid bits.
P4
0
0
P3
0
0
P2
0
0
P1
0
0
P0
0
1
Reverse line count
4 (1
×
4)
8 (2
×
4)
↓
124 (31
×
4)
128 (32
×
4)
↓
1
1
1
1
1
1
1
1
0
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1D15E06D03E000 | Direct RAM data display by display data RAM |
| S1D15E06T00A00A | Direct RAM data display by display data RAM |
| S1D15G10D08B000 | LCD drivers equipped with the liquid crystal drive power circuit |
| S1L50000 | HIGH DENSITY GATE ARRAY |
| S1L51253 | HIGH DENSITY GATE ARRAY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1D15E06D03E000 | 制造商:EPSON 制造商全稱:EPSON 功能描述:Direct RAM data display by display data RAM |
| S1D15E06T00A00A | 制造商:EPSON 制造商全稱:EPSON 功能描述:Direct RAM data display by display data RAM |
| S1D15G10D08B000 | 制造商:EPSON 制造商全稱:EPSON 功能描述:LCD drivers equipped with the liquid crystal drive power circuit |
| S1D19105 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:S1D19105d01b000 |
| S1D-1-E3 | 制造商:Vishay Semiconductors 功能描述:STANDARD RECOVERY POWER RECTIFIER FORWAR |
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