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參數(shù)資料
| 型號： | S1D15E06D03B000 |
| 廠商： | 愛普生（中國）有限公司 |
| 英文描述： | Direct RAM data display by display data RAM |
| 中文描述： | RAM數(shù)據(jù)顯示直接由顯示數(shù)據(jù)RAM |
| 文件頁數(shù)： | 15/74頁 |
| 文件大?。?/td> | 490K |
| 代理商： | S1D15E06D03B000 |
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S1D15E06 Series
12
EPSON
Rev. 2.1
6.1.4 Chip Selection
The S1D15E06 series has two chip select pins; CS1 and
CS2. MPU interface or serial interface is enabled only
when CS1 = LOW and CS2 = HIGH.
When the chip select pin is inactive, D0 to D5 are in the
state of high impedance, while A0, RD and WR inputs
are disabled. When serial interface is selected, the shift
register and counter are reset.
6.1.5 Access to display data RAM and
internal register
Access to S1D15E06 series viewed from the MPU side
is enabled only if the cycle time requirements are kept.
This does not required waiting time; hence, high-speed
data transfer is allowed.
Furthermore, at the time of data transfer with the MPU,
S1D15E06 series provides a kind of inter-LSI pipe line
processing via the bus holder accompanying the internal
data bus.
For example, when data is written to the display data
RAM by the MPU, the data is once held by the bus
holder. It is written to the display data RAM before the
next data write cycle comes.
On the other hand, when the MPU reads the content of
the display data RAM, it is read in the first data read
cycle (dummy), and the data is held in the bus holder.
Then it is read onto on the system bus from the bus
holder in the next data read cycle. Restrictions are
imposed on the display data RAM read sequence. When
the address has been set, specified address data is not
output to the Read command immediately after that.
The specified address data is output in the second data
reading. This must be carefully noted. Therefore, one
dummy read operation is mandatory subsequent to
address setting or write cycle. Fig. 6.2 illustrates this
relationship.
Fig. 6.1
* When the chip is inactive, the counter is reset to the initials state.
* Reading is not performed in the case of serial interface.
* For the SCL signal, a sufficient care must be taken against terminal reflection of the wiring and external noise.
Recommend to use an actual equipment to verify the operation.
CS2
SI
SCL
A0
CS1
D7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D6
D5
D4
D3
D2
D7
D6
D5
D4
D3
D2
D1
D0
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| S1D15E06D03E000 | Direct RAM data display by display data RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
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| S1D15E06D03E000 | 制造商:EPSON 制造商全稱:EPSON 功能描述:Direct RAM data display by display data RAM |
| S1D15E06T00A00A | 制造商:EPSON 制造商全稱:EPSON 功能描述:Direct RAM data display by display data RAM |
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