
Epson Research and Development
Vancouver Design Center
Page 107
Programming Notes and Examples
Issue Date: 01/02/05
S1D13505
X23A-G-003-07
Appendix A Supported Panel Values
A.1 Supported Panel Values
The following tables show related register data for different panels. All the examples are
based on 8 bpp and 2M bytes of 50 ns EDO-DRAM.
Note
The following settings may not reflect the ideal settings for your system configuration.
Power, speed, and cost requirements may dictate different starting parameters for your
system (e.g. 320x240@78Hz using 12MHz clock).
Table 12-1: Passive Single Panel @ 320x240 with
40MHz Pixel Clock
Register
Mono 4-Bit
320X240@60Hz
Mono 4-Bit
EL
320X240@60Hz
1000 0000
0000 0000
0010 0111
0001 0111
1110 1111
0000 0000
0011 1110
0000 1101
0000 0011
0000 0001
0000 0000
load LUT
Color 8-Bit
320X240@60Hz
Color 8-Bit
Format 2
320X240@60Hz
0001 1100
0000 0000
0010 0111
0001 0111
1110 1111
0000 0000
0011 1110
0000 1101
0000 0011
0000 0001
0000 0000
load LUT
Notes
REG[02h]
REG[03h]
REG[04h]
REG[05h]
REG[08h]
REG[09h]
REG[0Ah]
REG[0Dh]
REG[19h]
REG[1Bh]
REG[24h]
REG[26h]
0000 0000
0000 0000
0010 0111
0001 0111
1110 1111
0000 0000
0011 1110
0000 1101
0000 0011
0000 0001
0000 0000
load LUT
0001 0100
0000 0000
0010 0111
0001 0111
1110 1111
0000 0000
0011 1110
0000 1101
0000 0011
0000 0001
0000 0000
load LUT
set panel type
set MOD rate
set horizontal display width
set horizontal non-display period
set vertical display height bits 7-0
set vertical display height bits 9-8
set vertical non-display period
set 8 bpp and LCD enable
set MCLK and PCLK divide
disable half frame buffer
set Look-Up Table address to 0
load Look-Up Table
Table 12-2: Passive Single Panel @ 640x480 with
40MHz Pixel Clock
Register
Mono 8-Bit
640X480@60Hz
0001 0000
0000 0000
0100 1111
0000 0011
1101 1111
0000 0001
0000 0010
0000 1101
0000 0001
0000 0001
0000 0000
load LUT
Color 8-Bit
640X480@60Hz
0001 0100
0000 0000
0100 1111
0000 0011
1101 1111
0000 0001
0000 0010
0000 1101
0000 0001
0000 0001
0000 0000
load LUT
Color 16-Bit
640X480@60Hz
0010 0100
0000 0000
0100 1111
0000 0011
1101 1111
0000 0001
0000 0010
0000 1101
0000 0001
0000 0001
0000 0000
load LUT
Notes
REG[02h]
REG[03h]
REG[04h]
REG[05h]
REG[08h]
REG[09h]
REG[0Ah]
REG[0Dh]
REG[19h]
REG[1Bh]
REG[24h]
REG[26h]
set panel type
set MOD rate
set horizontal display width
set horizontal non-display period
set vertical display height bits 7-0
set vertical display height bits 9-8
set vertical non-display period
set 8 bpp and LCD enable
set MCLK and PCLK divide
disable half frame buffer
set Look-Up Table address to 0
load Look-Up Table