參數(shù)資料
型號(hào)： S1C60N08D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, UUC96
封裝： DIE-96
文件頁(yè)數(shù)： 2/28頁(yè)
文件大小： 325K
代理商： S1C60N08D
10
S1C60N08/60R08
s S1C60R08 ROM EMULATOR/ROM EMULATOR PROGRAMMER
The S1C60R08 has a built-in ROM emulator, which is constructed by RAM, to emulate mask ROM. The ROM
emulator is programmed from outside through the serial interface (programmer) circuit and then its data is read
by the CPU. This chapter explain the ROM emulator and the Programmer circuit.
q Configuration of ROM Emulator
The built-in ROM emulator is the same structure with the mask ROM built-in S1C60N08. And used for loading the
user-program. That has a capacity of 4,096 steps
× 12 bits. The program area consists of 16 (0–15) pages × 256
(00H–FFH) steps. After initial reset, the program beginning address is set to bank 0, page 1, step 00H. The
interrupt vector is allocated to page 1, steps 01H–0FH.
Step 00H
Step 0FH
Step 10H
Step FFH
12 bits
Program start address
Interrupt vector area
Bank 0
Page 0
Page 1
Page 2
Page 3
Page 15
Step 01H
The ROM emulator data is downloaded from an external Serial EEPROM through the Programmer circuit. After
power on or a HIGH pulse is input to the OTPRST pin, the ROM emulator data is initialized and downloading will
be started.
q Configuration of ROM Emulator Programmer
The ROM emulator data is written through the Programmer. The Programmer supports data transmit/receive
communication with Serial EEPROM, interface data error check and system reset signal generation.
VSS
CPU
VDD
OTPRST
SDA
SCL
ERROUT
Error Detect
Circuit
OSC1
RESET
S1C60R08
System reset
Configuration
flag
CPU and
peripheral circuit
ROM
Emulator
4,096
×12
bits
EEPROM
Interface
Circuit
A2
A1
A0
Serial
EEPROM
Terminals
The Programmer uses the following input/output terminals.
SCL:
Serial EEPROM control clock output terminal
SDA:
Serial EEPROM data transmit/receive terminal
ERROUT:
Data check result output terminal
OTPRST:
Data re-loading start input terminal
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