
1
OUTLINE
A-6
EPSON
S1C33209/221/222 PRODUCT PART
1.3.2 Pin Functions
Table 1.3.1
List of Pins for Power Supply System
Pin name
Pin No.
I/O
Pull-up
Function
QFP5-128
QFP15-128
VDD
11,77,114
8,74,111
–
Power supply (+) for the internal logic
VSS
2,25,42,57,
70,93,105,
107
127,22,39,
54,67,90,
102,104
–
Power supply (-); GND
VDDE
30,50,96
27,47,93
–
Power supply (+) for the I/O block
AVDDE
38
35
–
Analog system power supply (+); AVDDE = VDDE
Table 1.3.2
List of Pins for External Bus Interface Signals
Pin name
Pin No.
I/O
Pull-up
Function
QFP5-128
QFP15-128
A0
#BSL
67
64
O
–
A0:
Address bus (A0) when SBUSST(D3/0x4812E) = "0" (default)
#BSL:
Bus strobe (low byte) signal when SBUSST(D3/0x4812E) = "1"
A[23:1]
68,71–75,
79,81,83,
85–92,94,
95,97,
99–101
65,68–72,
76,78,80,
82–89,91,
92,94,96–98
O
–
Address bus (A1 to A23)
D[15:0]
10,13,15,17,
19,21,23,28,
29,41,43–48
7,10,12,14,
16,18,20,25,
26,38,40–45
I/O
–
Data bus (D0 to D15)
#CE10EX
60
57
O
–
Area 10 chip enable for external memory
* When CEFUNC[1:0] = "1x", this pin outputs #CE9+#CE10EX signal.
#CE10IN
76
73
O
–
Area 10 chip enable for internal ROM emulation
#CE9
#CE17
51
48
O
–
#CE9:
Area 9 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"
(default)
#CE17:
Area 17 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"
* When CEFUNC[1:0] = "1x", this pin outputs #CE17+#CE18 signal.
#CE8
#RAS1
#CE14
#RAS3
61
58
O
–
#CE8:
Area 8 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"
and A8DRA(D8/0x48128) = "0" (default)
#RAS1:
Area 8 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130) =
"00" and A8DRA(D8/0x48128) = "1"
#CE14:
Area 14 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"or
"1x" and A14DRA(D8/0x48122) = "0"
#RAS3:
Area 14 DRAM row strobewhen CEFUNC[1:0](D[A:9])/0x48130) =
"01"or "1x" and A14DRA(D8/0x48122) = "1"
#CE7
#RAS0
#CE13
#RAS2
53
50
O
–
#CE7:
Area 7 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"
and A7DRA(D7/0x48128) = "0" (default)
#RAS0:
Area 7 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130) =
"00" and A7DRA(D7/0x48128) = "1"
#CE13:
Area 13 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"or
"1x" and A13DRA(D7/0x48122) = "0"
#RAS2:
Area 13 DRAM row strobewhen CEFUNC[1:0](D[A:9])/0x48130) =
"01" or "1x" and A13DRA(D7/0x48122) = "1"
#CE6
55
52
O
–
Area 6 chip enable
* When CEFUNC[1:0] = "1x", this pin outputs #CE7+#CE8 signal.
#CE5
#CE15
62
59
O
–
#CE5:
Area 5 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"
(default)
#CE15:
Area 15 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"
* When CEFUNC[1:0] = "1x", this pin outputs #CE15+#CE16 signal.