
Dot Matrix LCD Driver
S-4543A
Seiko Instruments Inc.
13
3. Status
The internal operation status of S-4543A is monitored for four kinds of status. The status is output in D
4
through
D
7
. For the monitoring method and function, refer to the Command functions section.
E1 and E2 cannot be activated at the same time during status reading.
Table 12 Internal Operation Status
Item
Output pin
D
7
D
6
D
5
Status
Busy flag
ADC select
Display
ON/OFF
Reset
“1”: Command operation, Reset operation “0“: Command ready
“1”:
Forward
“1”: Display all-lit
“0”: Reverse
“0”: Normal display status
D
4
“1”: Resetting
“0”: Normal operation status
4. Busy Flag
During internal operation, for example command operation, the busy flag is “1”, and commands other than Status
Read are not received. The Busy flag is output in D7 through the Status Read command. When accessing the
S-4543A by the signal which specifies the value of read cycle and write cycle timing, the busy flag “0” is not
required to be confirmed. Since busy flag check is not necessary, the load on MPU can be reduced.
5. Data Bus
Table 13 Data Bus
68 family
R/WX
1
Read from Display Data RAM
0
Write to Display Data RAM
1
Status Read
0
Command Read to internal register
A
0
Operation
1
1
0
0
6. Display Data RAM
The S-4543A has Display Data RAM (8 bits X 4 pages X 122 columns + 120 columns for icon =4026 bits). It is
possible to use the not-used area for display as normal SRAM. The Display Data RAM is in dual port RAM and
enables access from the MPU through Page address and Column address. To the LCD driver side, the one line’s
common output is read by Line address. The correlation between Page address, Column address, and Line
address is shown in Figure 7.
The displayed data RAM is made of dual-port RAM. The read/write access from the MPU interface is performed
independently of the read access to the liquid display. The read/write access to displayed data from the MPU is
done by a command. Data is read out to the liquid crystal display in synchronism with the liquid crystal display
clock.
At the moment power is turned on, the contents of the displayed data RAM are uncertain. Following turning on
power, clear the display RAM or write the displayed data with display OFF and then turn ON the display.
The displayed data RAM is divided into two parts by E1 and E2. The displayed data can be written into the
column address corresponding to SEG0-SEG60 by E1. E2 enables data writing into the column address
corresponding to SEG61-SEG119.