參數(shù)資料
型號(hào)： S-4543A
廠商： Seiko Instruments Inc.
英文描述： Dot Matrix LCD Driver(點(diǎn)陣LCD驅(qū)動(dòng)器)
中文描述： 點(diǎn)陣LCD驅(qū)動(dòng)器（點(diǎn)陣液晶驅(qū)動(dòng)器）
文件頁數(shù)： 15/27頁
文件大小： 163K
代理商： S-4543A
Dot Matrix LCD Driver
S-4543A
14
Seiko Instruments Inc.
7. Reading and Writing of Display Data
The S-4543A reads and writes the display data through the internal bus holder. The display data is read to the
bus holder from the display data RAM, and in the next read cycle on the data bus. Therefore, a dummy read
cycle is needed before the first read cycle. When reading the display data after the address set and the data write
cycle, a dummy read is needed. Since the reading of the display data is executed using this bus holder, it is
possible to read the data at high speed.
Display data is written to the display data RAM through the bus holder within a write cycle. Therefore, writing the
display data does not need a dummy cycle.
The displayed data is lit and unlit in the states “1” and “0”, respectively.
8. Column Address
The column address of the Display Data RAM is used for reading/writing displayed data from/to the MPU. The
column address is set by a command. When the displayed data RAM is accessed by the MPU, the address
increments by one. When the most significant address of the column address is read/written, an invalid address
is selected and it does not increment.
9. Page Address
The display RAM is composed of five pages. When accessing the display data RAM from MPU, the page of the
display data RAM is set a command.
10. CR Oscillation Circuit
It incorporates a CR oscillator which generates the clock for display.
Oscillation frequency is approximately 18 kHz at R
f
1 M
.
11. LCD Driving Circuit
The S-4543A generates a liquid crystal drive waveform of 2-frame AC drive system (type B). See Figure 8, “
Liquid Crystal Drive Output Waveform.”
12. Display Timing Circuit
It generates the clock by the CR oscillator circuit or an external input for the timings of the liquid crystal drive. See
Figure 8.
The frame frequency differs depending upon the selection of 1/32 or 1/33 duty ratio.
Table 15 Frame Frequency
Duty
Frame Frequency f
OSC
=18 kHz
1/32 duty
70.31 Hz
1/33 duty
68.18 Hz
13
.
Line Address
This is the address for reading the LCD RAM data to the LCD data latch. The line address is incremented
synchronizing with the common output. Further, the display start line which is output to COM0 can be set by a
command.
14. Display Data Latch
The display data latch is the circuit for latching one line’s display data from the display RAM. The display data is
output from this latch to the LCD drive circuit. Since the display ON/OFF and the display All-Lit ON/OFF control
the display data latch, it has no effect on the display RAM data.
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參數(shù)描述
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