參數(shù)資料
型號: S-35399A03-J8T2U
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO8
封裝: HALOGEN FREE AND LEAD FREE, SOP-8
文件頁數(shù): 26/53頁
文件大?。?/td> 472K
代理商: S-35399A03-J8T2U
2-WIRE REAL-TIME CLOCK
S-35399A03
Rev.2.0_00
Seiko Instruments Inc.
32
Serial Interface
The S-35399A03 receives various commands via I
2C-bus serial interface to Read/Write data. Regarding transmission is as
follows.
1. Start condition
A start condition is when the SDA line changes “H” to “L” when the SCL line is in “H”, so that the access starts.
2. Stop condition
A stop condition is when the SDA line changes “L” to “H” when the SCL line is in “H”, and the access stops, so that the
S-35399A03 gets standby.
tSU.STA
tHD.STA
tSU.STO
Start condition
Stop condition
SCL
SDA
Figure 33 Start/Stop Conditions
3. Data transmission and acknowledgment signal
Data transmission is performed for every 1-byte, after detecting a start condition. Transmit data while the SCL line is in
“L”, and be careful of spec of tSU.DAT and tHD. DAT when changing the SDA line. If the SDA line changes while the SCL line
is in “H”, the data will be recognized as start/stop condition in spite of data transmission. Note that by this case, the
access will be interrupted.
During data transmission, every moment receiving 1-byte data, the devices which work for receiving data send an
acknowledgment signal back. For example, as seen in Figure 34, in case that the S-35399A03 is the device working for
receiving data and the master device is the one working for sending data; when the 8-bit clock pulse falls, the master
device releases the SDA line. After that, the S-35399A03 sends an acknowledgment signal back, and set the SDA line
to “L” at the 9-bit clock pulse. The S-35399A03 does not output an acknowledgment signal is that the access is not
being done regularly.
1
8
9
Output acknowledgment
(“L” active)
tPD
Start condition
SCL
(Input from
S-35399A03)
SDA
(Output from
master device)
SDA
(Output from
S-35399A03)
SDA is released
tSU.DAT
tHD.DAT
High-Z
Figure 34 Output Timing of Acknowledgment Signal
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