參數(shù)資料
型號: S-35180AT8T1
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: REAL TIME CLOCK, PDSO8
封裝: TSSOP-8
文件頁數(shù): 8/46頁
文件大小: 498K
代理商: S-35180AT8T1
3-WIRE REAL-TIME CLOCK
S-35180A
Rev.2.0_00
Seiko Instruments Inc.
16
Power Supply Voltage Detector
S-35180A has an internal power supply voltage detector, which monitors drops in the power supply voltage
by reading the BLD flag. This circuit samples the voltage for only 15.6 ms per second. If the power supply
voltage drops below the detection voltage (VDET), the BLD latch circuit latches the “H” level, bit 6 (BLD flag)
of internal status register_1 is set to “1”, and sampling stops. Once “1” is detected in the BLD flag, no
detection operation is performed unless initialization is performed or the BLD flag is read by the status
register_1 access command, and “1” is held in the BLD flag. Sampling resumes only when the subsequent
communication action is initialization or BLD flag read.
In addition, if this BLD flag is “1” after the power supply voltage is recovered, it must be initialized.
Caution In case the power supply voltage falls and returns after the latch circuit latches “H”, the
BLD flag can be read as “1” by a status register_1 accsess command first. After that the
sampling is resumed and the read-out of the next BLD flag is performed, the BLD flag is
reset and read as “0”. Refer to the timing chart below.
VDD
Latch circuit
output
BLD flag
VDET
1 s
Stop
(0)
(1)
(0)
Status register_1
reading
Sampling pulse
Figure 18 Timing of Power Supply Voltage Detector
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