參數(shù)資料
型號(hào): S-3511A
廠商: Seiko Instruments Inc.
英文描述: CMOS Real-Time Clock IC(3 Lines)(3線,CMOS實(shí)時(shí)時(shí)鐘芯片)
中文描述: CMOS實(shí)時(shí)時(shí)鐘IC(3線)(3線,實(shí)時(shí)時(shí)鐘芯片的CMOS)
文件頁(yè)數(shù): 14/31頁(yè)
文件大小: 183K
代理商: S-3511A
Real-Time Clock
S-3511A
Seiko Instruments Inc.
13
6.
Power voltage detecting circuit
S-3511A has an internal power voltage detecting circuit. This circuit gives sampling movement for only 15.6msec. once a second.
If the power voltage decreases below the detected voltage (VDET), sampling movement stops. Only when subsequent
communication is of the status read command, the output of the latch circuit is transferred to the sift register and the sampling
movement is resumed.
Decrease in power voltage can be monitored by reading the POWER flag.
That is to say, once decrease in power voltage is detected, any detecting operation is not performed and "H" is held unless you
perform initialization or send the status read command.
[Note]
When power voltage is increased and the first read operation is performed after decrease in power voltage occurs and the latch
circuit latches "H", "1" can be read on the POWER flag. However, if the next read operation is performed after the sampling of the
detecting circuit, the POWER flag is reset since sampling is subsequently allowed. See the timing diagram below.
Latch circuit
output
Sampling pulse
(0)
1sec
1sec
Stop
Stop
Stop
(1)
(1)
(1) (1)
(1) (1)
(0)
VDD
POWER flag
V
DET
Communication
Communication
Sampling pulse
Carry pulse
1sec
1sec
(1)
(0)
Latch circuit
output
POWER flag
[Timing of sampling pulse]
0.5sec
0.5sec
7.8mse
Carry-up timing
15.6mse
Latch timing
1Hz
V
DET
Sampling pulse
Stop
Stop
Stop
Stop
(1)
(0)
Figure 13 Timing of the power voltage detecting circuit
VDD
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