
REAL-TIME CLOCK
S-3510
Series
8
Seiko Instruments Inc.
Operation
(1) Initialization
When the power is switched on, the POW flag is assigned via the power-on detector. ALWAYS TURN the CS to
”
L.
”
Regardless of the logic of the POW flag, initialization must be executed. Therefore, ALWAYS SEND the RESET command
(10101010) from the CPU.
This allows the divider, counter and status register of the S-3510 series to be reset. Namely, the second, minute, hour,
day, date, month, and year (00 sec., 00 min., 00 hr., Sunday (1), January (01), 00 year) are set, and the counter starts to
operate upon the falling edge of the CS.
(2) Write to the Status Register
The S-3510 series is provided with a 4-bit status register. To write the data in the register, send the STATUS WRITE
command (1011D3D2D1D0). This data is retrieved in synchronization with the falling edge of the CS.
Upon initialization, (D3, D2, D1, D0) is set to (1, 0, 1, 0).
In other words,
In the S-3510ANFJX, the S-3510ACFJA, 1 Hz is output from TP
OUT
, and the status is set to the 24-hour display
mode.
In the S-3510AEFJX, the S-3510ADFJA, the S-3510AFFJA, 32768 Hz is output from TP
OUT
, and the status is set to
the 24-hour display mode.
When initialization is not executed, the data of the status register is not specified. ALWAYS execute initialization when
switching on the power.
D1
D2
SIO
Input
CS
SCK
X
1
0
1
0
1
0
1
0
Reset
Figure 6
Free bit:
Stores the information according to a user-specified memory
bit. It does not affect the function of the timer. Reset to
”
0
”
during initialization.
TP
OUT
output frequency-select bit (*)
In the S-3510ANFJA, the S-3510ACFJX
0: 32768 Hz
1: 1 Hz
In the S-3510AEFJA, the S-3510ADFJA, the S-3510AFFJA
0, 1: 32768 Hz (It can be used as Free bit)
TP
OUT
enable bit
In the S-3510ANFJX, the S-3510ACFJX
0: Output
1: High impedance
In the S-3510AEFJA, the S-3510ADFJA, the S-3510AFFJA
0, 1: Output (It can be used as Free bit)
12/24-hour display change bit 0: 12-hour display
1: 24-hour display
D3
D2
D1
D0
(*)
PLEASE NOTE that when the frequency-select bit is rewritten during operation, the first pulse generated immediately after the CS is turned to
“
L
”
cannot be output at the correct frequency.
CS
X
1
0
1
D3
1
D0
SIO
SCK
Figure 7