參數(shù)資料
型號: S-3510
廠商: Seiko Instruments Inc.
英文描述: CMOS Real-Time Clock IC (3 Lines)(3線,CMOS實時時鐘芯片)
中文描述: CMOS實時時鐘IC(3線)(3線,實時時鐘芯片的CMOS)
文件頁數(shù): 10/24頁
文件大?。?/td> 166K
代理商: S-3510
REAL-TIME CLOCK
S-3510
Series
Seiko Instruments Inc.
9
(3) Data Read
The time data can be read by sending the READ command after the CS goes “H.” The data is output in order of the LSB of
the day or year.
After the READ command is interpreted, the time data is transmitted from the counter to the shift register. In
synchronization with the falling edge of the 9th clock, the SIO status changes from input to output, and the LSB of the timer
register is output. After then, in synchronization with the falling edge of the clock, the time data is output from the shift
register.
If the power supply voltage detector activates, the MSB (BLD bit) is set to”1,” which allows the power supply voltage to be
monitored. For more details, refer to the “(6) Voltage Detector”.
(4) Data Write
Sending the WRITE command after the CS changes from “L” to”H” halts the update operation and resets the frequency
divider. This allows the time data to be written. The data is input in order of the LSB of the day or year. The time data
transmitted from the SIO is written in the shift register in synchronization with the rising edge of the clock. After transmission of
the minute data has been completed, the currently-stored data is transmitted to the counter during the period of the transmission
of the second data, and the month-end correction is executed. The second data is transmitted from the shift register to the
second counter in synchronization with the point where the CS changes from “H” to”L.” Accordingly, the second data error
processing is not performed. Turning the CS to “L” allows the divider to run and update operation to start. One second after,
the carry-up signal is transmitted to the second counter. If non-existent data is written in the second counter, the second
counter is set to “00,” and the carry-up signal is transmitted to the minute counter.
WWW
0 1 2
m
6
m
5
12
24
m
6
BLD
T
P
E
N
T
P
F
F
R
E
64
9
1
S S S S S S
1 2 3 4 5 6
S
0
P
O
C
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
X
X
X
X
0
1
1
1
X
M
0
Output Mode Change
READ1 mode
CS
SCK
SI
READ 2 mode
40
9
1
S S S S S S
1 2 3 4 5 6
S
0
P
O
C
X
X
X
X
1
1
1
1
X
BLD
H
0
m
5
CS
SCK
SIO
T
e
s
t
Figure 8
Output Mode Change
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