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參數(shù)資料
| 型號(hào)： | RV5C338A-E2 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | DIODE ZENER SINGLE 200mW 8.2Vz 20mA-Izt 0.02549 0.1uA-Ir 6.5 SOD-323 3K/REEL |
| 中文描述： | REAL TIME CLOCK, PDSO10 |
| 封裝： | 4 X 2.90 MM, 1.20 MM HEIGHT, SSOP-10 |
| 文件頁數(shù)： | 17/52頁 |
| 文件大?。?/td> | 440K |
| 代理商： | RV5C338A-E2 |
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5C338A
14
2.2-4 XSTP
Oscillator Halt Sensing Bit
CLEN1
Description
0
Enabling the 32-kHz clock output
1
Disabling the 32-kHz clock output
2.2-5 CLEN1
32-kHz Clock Output Bit 1
(Default setting)
CTFG
Description
0
Periodic interrupt output “H” (OFF)
1
Periodic interrupt output “L” (ON)
2.2-6 CTFG
Periodic Interrupt Flag Bit
(Default setting)
The CTFG bit is set to 1 when the periodic interrupt signals are output from the INTR pin (“L”). The CTFG bit
accepts only the writing of 0 in the level mode, which disables (“H”) the INTR pin until it is enabled (“L”) again in
the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.
Setting the CLEN1 bit or the CLEN2 bit (D4 in control register 1) to 0, and the CLKC pin to high specifies
generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the
32KOUT pin. Conversely, setting both the CLEN1 bit and the CLEN2 bit to 1 or the CLKC pin to low specifies
disabling (“L”) such output.
The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator. The oscillation halt sensing circuit
operates only when the CE pin is “L”.
· The XSTP bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events as pow-
er-on from 0 volts and a drop in supply voltage. The XSTP bit will hold the setting of 1 even after the restart of
oscillation. As such, the XSTP bit can be applied to judge the validity of clock and calendar data after power-on or
a drop in supply voltage.
· When the XSTP bit is set to 1, all bits will be reset to 0 in the oscillation adjustment register, control register 1, and
control register 2, stopping the output from the INTR pin and starting the output of 32.768-kHz clock pulses from
the 32KOUT pin.
(32KOUT output is disabled when CLKC pin is set to low.)
· The XSTP bit accepts only the writing of 0, which restarts the oscillation halt sensing circuit. Conversely, setting
the XSTP bit to 1 causes no event.
XSTP
Description
0
Sensing a normal condition of oscillation
1
Sensing a halt of oscillation
(Default setting)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| RV5C339 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MONITORING FUNCTION |
| RV5C339A | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MONITORING FUNCTION |
| RV5C339A_03 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:3-WIRE SERIAL INTERFACE REAL-TIME CLOCK IC WITH VOLTAGE MONITORING FUNCTION |
| RV5C339A-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MONITORING FUNCTION |
| RV5C348A | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:4-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MONITORING FUNCTION |
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