參數(shù)資料
型號(hào): RV5C338A-E2
廠商: RICOH COMPANY LTD
元件分類: XO, clock
英文描述: DIODE ZENER SINGLE 200mW 8.2Vz 20mA-Izt 0.02549 0.1uA-Ir 6.5 SOD-323 3K/REEL
中文描述: REAL TIME CLOCK, PDSO10
封裝: 4 X 2.90 MM, 1.20 MM HEIGHT, SSOP-10
文件頁數(shù): 15/52頁
文件大?。?/td> 440K
代理商: RV5C338A-E2
R
×
5C338A
12
Relation Between the Mode Waveform and the CTFG Bit
Pulse mode
Approx. 92
μ
s
CTFG bit
INTR pin
(Increment of second counter)
Rewriting of the second counter
Level mode
Setting CTFG bit to 0
(Increment of
second counter)
Setting CTFG bit to 0
CTFG bit
INTR pin
(Increment of
second counter)
(Increment of
second counter)
*
) In the pulse mode, the increment of the second counter is delayed by approximately 92μs from the falling edge of clock pulses. Consequently, time
readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.
Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTR pin low.
2) Level Mode : periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1
hour, and 1 month. The increment of the second counter is synchronized with the falling edge of
periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of
1 second are output in synchronization with the increment of the second counter as illustrated in
the timing chart below.
3) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20 seconds as follows:
Pulse Mode : the “L” period of output pulses will increment or decrement by a maximum of ±3.784ms.
For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.
Level Mode : a periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784ms.
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