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參數(shù)資料
| 型號： | RS5C348A-E2 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | Real-Time Clock |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO10 |
| 封裝： | 6.40 X 3.50 MM, 1.25 MM HEIGHT, 0.5 MM PITCH, SSOP-10 |
| 文件頁數(shù)： | 18/53頁 |
| 文件大?。?/td> | 452K |
| 代理商： | RS5C348A-E2 |
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15
R
×
5C348A/B
2.2-4 XSTP
Oscillation Halt Sensing Bit
CLEN1
Description
0
Enabling the 32-kHz clock output
1
Disabling the 32-kHz clock output
2.2-5 CLEN1 (R
×
5C348A)
32-kHz Clock Output Bit 1
(Default setting)
For the R
×
5C348A, setting the CLEN1 bit or the CLEN2 bit (D4 in control register 1) to 0 specifies generating clock
pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.
Conversely, setting both the CLEN1 bit and the CLEN2 bit to 1 specifies disabling (“H”) such output.
The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator. The oscillation halt sensing circuit
operates only when the CE pin is
“L”.
· The XSTP bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events as
power-on from 0 volts and a drop in supply voltage. The XSTP bit will hold the setting of 1 even after the restart of
oscillation. As such, the XSTP bit can be applied to judge the validity of clock and calendar data after power-on or
a drop in supply voltage.
· When the XSTP bit is set to 1, all bits will be reset to 0 in the oscillation adjustment register, control register 1,
and control register 2, stopping the output from the INTR pin and starting the output of 32.768-kHz clock pulses
from the 32KOUT pin.
· The XSTP bit accepts only the writing of 0, which restarts the oscillation halt sensing circuit. Conversely, setting
the XSTP bit to 1 causes no event.
· It is recommendable to frequently check the XSTP bit for setting errors or data garbles, which may seriously
affect the operation of the R
×
5C348A/B.
XSTP
Description
0
Sensing a normal condition of oscillation
1
Sensing a halt of oscillation
(Default setting)
SCRATCH2(R
×
5C348B)
Description
0
1
SCRATCH2 (R
×
5C348B)
Scratch Bit 2
(Default setting)
For the R
×
5C348B, this bit is a scratch bit. The SCRATCH2 bit will accept the reading and writing of 0 and 1. The
SCRATCH2 bit will set to 0 when the XSTP bit is set to 1.
相關PDF資料 |
PDF描述 |
|---|---|
| RS5C348B-E2 | Real-Time Clock |
| RT1710B6 | LVDS & LVPECL FPGA Terminator RoHS Compliant Parts Available |
| RT1710B7 | LVDS & LVPECL FPGA Terminator RoHS Compliant Parts Available |
| RT1720B7 | LVDS & LVPECL FPGA Terminator RoHS Compliant Parts Available |
| RT1721B6 | LVDS & LVPECL FPGA Terminator RoHS Compliant Parts Available |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| RS5C348B | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:4-WIRE SERIAL INTERFACE |
| RS5C348B-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:Real-Time Clock |
| RS5C372A | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:I2C bus SERIAL INTERFACE REAL-TIME CLOCK ICs |
| RS5C372B | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:I2C-bus Serial Interface Real Time Clock (8pin SSOP) |
| RS5C372B-E1 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:I2C-bus Serial Interface Real Time Clock (8pin SSOP) |
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