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參數資料
| 型號： | RS5C338A-E2 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | DIODE ZENER SINGLE 500mW 2.4Vz 0.05mA-Izt 0.05 2uA-Ir 1 SOD-123 3K/REEL |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO10 |
| 封裝： | 6.40 X 3.50 MM, 1.25 MM HEIGHT, SSOP-10 |
| 文件頁數： | 37/52頁 |
| 文件大小： | 440K |
| 代理商： | RS5C338A-E2 |
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R
×
5C338A
34
4. Alarm and Periodic Interrupt
The R
×
5C338A incorporate the alarm circuit and the periodic interrupt circuit that are configured to generate alarm
signals and periodic interrupt signals, respectively, for output from the INTR pin as described below.
1)Alarm Circuit
The alarm interrupt circuit is configured to generate alarm signals for output from the INTR, which is driven low
(enabled) upon the occurrence of a match between current time read by the time counters (the day-of-week, hour,
and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers intended for the day-
of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and minute digit set-
tings).
2)Periodic Interrupt Circuit
The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals
in the level mode for output from the INTR pin depending on the CT
2
, CT
1
, and CT
0
bit settings in the control reg-
ister 1.
The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the
control register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT
2
, CT
1
, and CT
0
bits in the
control register 1) as listed in the table below.
Flag bits
Enable bits
Alarm signals
(under control of Alarm_W registers)
WAFG bit
(D1 at Address Fh)
WALE bit
(D7 at Address Eh)
Alarm signals
(under control of Alarm_D registers)
DAFG bit
DALE bit
(D0 at Address Fh)
(D6 at Address Eh)
Periodic interrupt signals
CTFG bit
CT
2
, CT
1
, and CT
0
bits (D2 to D0 at Address Eh)
(these bit settings of 0 disable the periodic interrupt circuit)
(D2 at Address Fh)
· At power-on, when the WALE, DALE, CT
2
, CT
1
, and CT
0
bits are set to 0 in the control register 1, the INTR pin is
driven high (disabled).
· When two or more types of interrupt signals are output simultaneously from the INTR pin, the output from the
INTR pin becomes an OR waveform of their negative logic.
Alarm_W
Alarm_D
INTR
In this event, which type of interrupt signal is output from the INTR pin can be confirmed by reading the
WAFG, DAFG, and CTFG bit settings in the control register 2.
Example: Combined Output of Alarm Interrupt Signals from the INTR pin Under Control of Alarm_D and
Alarm_W Registers
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相關代理商/技術參數 |
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|---|---|
| RS5C348A | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:4-WIRE SERIAL INTERFACE |
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| RS5C348B | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:4-WIRE SERIAL INTERFACE |
| RS5C348B-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:Real-Time Clock |
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