參數(shù)資料
型號: RS5C338A-E2
廠商: RICOH COMPANY LTD
元件分類: XO, clock
英文描述: DIODE ZENER SINGLE 500mW 2.4Vz 0.05mA-Izt 0.05 2uA-Ir 1 SOD-123 3K/REEL
中文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO10
封裝: 6.40 X 3.50 MM, 1.25 MM HEIGHT, SSOP-10
文件頁數(shù): 22/52頁
文件大小: 440K
代理商: RS5C338A-E2
19
R
×
5C338A
2.7 Alarm_W Register (at Address 8h to Ah)
D7
D6
D5
D4
D3
D2
D1
D0
WM
40
WM
20
WM
10
WM
8
WM
4
WM
2
WM
1
0
WM
40
WM
20
WM
10
WM
8
WM
4
WM
2
WM
1
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
(For writing)
(For reading)
Default settings*
2.7-1 Alarm_W Minute Register (at Address 8h)
D7
D6
D5
D4
D3
D2
D1
D0
WH
20
,WP/A
WH
10
WH
8
WH
4
WH
2
WH
1
0
0
WH
20
,WP/A
WH
10
WH
8
WH
4
WH
2
WH
1
0
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
(For writing)
(For reading)
Default settings*
2.7-2 Alarm_W Hour Register (at Address 9h)
D7
D6
D5
D4
D3
D2
D1
D0
WW
6
WW
5
WW
4
WW
3
WW
2
WW
1
WW
0
0
WW
6
WW
5
WW
4
WW
3
WW
2
WW
1
WW
0
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
(For writing)
(For reading)
Default settings*
2.7-3 Alarm_W Day-of-week Register (at Address Ah)
· The D5 bit of the Alarm_W hour register represents WP/A when the 12-hour mode is selected (0 for a.m. and 1
for p.m.). and WH
20
when the 24-hour mode is selected (tens in the hour digits).
· The Alarm _W registers should not have any non-existent alarm time settings. (Note that any mismatch between
current time and preset alarm time specified by the Alarm_W registers may disable the alarm circuit.)
· When the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively (see “2.1-2
12/24: 12-/24-hour Mode Selection Bit”).
· WW
0
to WW
6
correspond to W
4
, W
2
, and W
1
of the day-of-week counter with settings ranging from (0, 0, 0) to (1,
1, 0).
· WW
0
to WW
6
with respective settings of 0 disable the outputs of the Alarm_W registers.
*
) Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.
An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3ppm (2 / (32768
×
20=3.051ppm). Conversely, a decrease of two clock pulses once per 20 seconds causes a time count gain of 3ppm.
Consequently, deviations in time counts can be corrected with a precision of ±1.5ppm. Note that the oscillation
adjustment circuit is configured to correct deviations in time counts and not the oscillation frequency of the 32.768-
kHz clock pulses. For further details, see “USAGE, 2.4 Oscillation Adjustment Circuit”.
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