參數(shù)資料
型號(hào): RS5C317B
廠商: RICOH COMPANY LTD
元件分類: XO, clock
英文描述: ULTRA-COMPACT HIGH PERFORMANCE SERIAL REAL-TIME CLOCK ICs
中文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO14
封裝: 0.65 MM PITCH, SSOP-14
文件頁(yè)數(shù): 18/40頁(yè)
文件大小: 309K
代理商: RS5C317B
RS5C317A/B
14
CLKC pin
CLEN bit
32KOUT output
L (open)
0 (prohibited to write)
High impedance
H
0
32kHz clock output
H
1
High impedance
D3
D2
D1
D0
S
8
S
4
S
2
S
1
(For read/write) 1-second time digit
(at0h)
*
M
8
S
40
S
20
S
10
(For read/write) 10-second time digit
(at1h)
M
4
M
2
M
1
(For read/write) 1-minute time digit
(at2h)
*
H
8
M
40
M
20
M
10
(For read/write) 10-minute time digit
(at3h)
H
4
H
2
H
1
(For read/write) 1-hour time digit
(at4h)
*
*
P/A or H
20
H
10
(For read/write) 10-hour time digit
(at5h)
*
6) Timing diagram for TMOUT
*
7) Writing operation to the timer register makes the timer counter to start operation with resetting.
TMR
1
TMR
1
0.977ms
MAX. T1
T2
T3
TMOUT
D3
D2
D1
D0
*
*
*
CLEN
(For read/write)
*
1) The “
*
” mark indicates data which are set to 0 for read cycle and not set for write cycle.
*
2) (CLEN) control bit for 32kHz output
The CLEN bit is set to 0 when the XSTP=1. CLEN is not writable and set to 0 when CLKC pin level low/open.
*
3) 32KOUT condition
2.6 32kHz control register (BANK 1, at Ah)
3. Counters
3.1 Clock counter (BANK 0, at 0h-5h)
*
1) The “
*
” mark indicates data which are set to 0 for read cycle and not set for write cycle.
*
2) Any carry to 1-second digits from the second counter is disabled when the WTEN bit (of the control register 1) is set to 0.
*
3) Time digit display (BCD code):
Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00.
Minute digits : Range from 00 to 59 and carried to hour digits when incremented from 59 to 00.
Hour digits
: Range as shown in the section on the 12/24 bit and carried to day and day-of-the-week digits when incremented from 11 p.m. to 12
a.m. or 23 to 00.
*
4) Any registered imaginary time should be replaced with actual time as carrying to such registered imaginary time digits from lower-order ones cause
the clock counter to malfunction.
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