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參數(shù)資料
| 型號： | RP5C62 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | REAL-TIME CLOCK |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDIP18 |
| 封裝： | DIP-18 |
| 文件頁數(shù)： | 28/48頁 |
| 文件大?。?/td> | 419K |
| 代理商： | RP5C62 |
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RP/RF/RS5C62
Timer clock selection register and TMFG bit
(See “2.9 Timer Clock Selection Register”)
TMR bit
(See “2.1 Control Register 1”)
Elements Involved in Timer
Reference
Considerations in Using XSTP Bit
7. Detection of Stop of Oscillation
The stop of oscillation can be detected by monitoring the XSTP bit in the control register 2. Namely, the XSTP
bit is switched from “0” to “1” upon detection of the stop of oscillation. This principle can be used to check the valid-
ity of time data.
(The stop of oscillation can also be detected by using the software-controlled processes described in 11.1.2
Initialization Subject to Setting of XSTP Bit. “Initialization at Power-on”.)
Power-on from 0V
*
1
XSTP
Stop of oscillation
Setting the XSTP bit to “0”
(During oscillation)
Restart of oscillation
*
2
*
1) The XSTP bit is set to “1” at power-on from 0V. Note that the XSTP bit may be locked at instantaneous power disconnection.
*
2) Once the stop of oscillation has been detected, the XSTP bit is kept at “1” even after the restart of oscillation.
It is recommended to update the settings of the timer clock selection register at regular time intervals to
improve the stability of timer operation.
Ensure error-free detection of the stop of oscillation by:
1) Preventing the VDD pin input from making instantaneous power disconnection.
2) Preventing the crystal oscillators causing condensation.
3) Preventing the crystal oscillators from causing noises on the PCB.
4) Preventing the individual pins from being impressed with voltage exceeding the maximum rating.
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