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參數(shù)資料
| 型號： | RP5C62 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | REAL-TIME CLOCK |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDIP18 |
| 封裝： | DIP-18 |
| 文件頁數(shù)： | 18/48頁 |
| 文件大?。?/td> | 419K |
| 代理商： | RP5C62 |
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14
RP/RF/RS5C62
*
1) Only the TM
3
bit is intended for read operation. The D0 bit is always read as “TMFG”. The D2 and D1 bits are always read as “0”.
*
2) The TM
3
to TM
0
bits are used to set cycles for the counters as shown in the table below.
2.9 Timer Clock Selection Register (BANK1 at “Ch”)
D3
D2
D1
D0
0
0
TMFG
TM
3
TM
3
TM
2
TM
1
TM
0
(For write operation)
(For read operation)
*
1
Timer counter cycle setting bit (TM
3
to TM
0
) *
2
Timer output indication bit (TMFG) *
3
T1 : Maximum time during which timer output is disabled after timer resetting.
(Timer reset occurs upon setting the TMR bit to “1” in the control register 1.)
(Timer output occurs upon driving low the TMOUT pin output.)
T2 : Time between timer output and cycle setting during timer resetting (upon setting the TM
3
bit to “0” ),
or timer resetting, or transition of the CE pin input from its low to high levels.
T3 : Timer output cycle without timer reset.
TM
3
TM
2
TM
1
TM
0
T1
T2
T3
(Watchdog timer cycle)
(Output time after timer resetting)
(Free-running timer cycle)
0
*
*
*
Timer output disabled
(TMOUT pin output turned off)
Timer output disabled
(TMOUT pin output turned off)
Timer output disabled
(TMOUT pin output turned off)
1
0
0
0
562ms
562 to 626ms
625ms
1
0
0
1
281ms
281 to 313ms
312.5ms
1
0
1
0
140ms
140 to 157ms
156.3ms
1
0
1
1
70.3ms
70.3 to 78.2ms
78.13ms
1
1
0
0
35.1ms
35.1 to 39.1ms
39.06ms
1
1
0
1
17.5ms
17.5 to 19.6ms
19.53ms
1
1
1
0
8.78ms
8.78 to 9.77ms
9.766ms
1
1
1
1
4.39ms
4.39 to 4.89ms
4.883ms
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