參數(shù)資料
型號(hào)： RH8053GC033512
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 19/81頁
文件大小： 598K
代理商： RH8053GC033512
Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Order Number#249563-001
Datasheet
19
Table 7. Recommended Resistors for Mobile Intel Celeron Processor Signals
Recommended
Resistor Value (
W
)
Mobile Intel Celeron Processor Signal
1, 2
10 pull-down
BREQ0#
3
RESET#
4
56.2 pull-up
150 pull-up
PICD[1:0], TDI, TDO
270 pull-up
SMI#
680 pull-up
STPCLK#
1K pull-up
INIT#, TCK, TMS
1K pull-down
TRST#
1.5K pull-up
A20M#, FERR#, FLUSH#, IERR#, IGNNE#, LINT0/INTR,
LINT1/NMI, PREQ#, PWRGOOD, SLP#
NOTES:
1.
The recommendations above are only for signals that are being used. These recommendations are
maximum values only; stronger pull-ups may be used. Pull-ups for the signals driven by the chipset should
not violate the chipset specification. Refer to Section 3.1.4 for the required pull-up or pull-down resistors for
signals that are not being used.
Open-drain signals must never violate the undershoot specification in Section 4.3. Use stronger pull-ups if
there is too much undershoot.
A pull-down on BREQ0# is an alternative to having the central agent to drive BREQ0# low at reset.
A 56.2
1% terminating resistor connected to V
CCT
is required.
2.
3.
4.
3.1.1
Power Sequencing Requirements
The mobile Intel Celeron processor has no power sequencing requirements. Intel recommends that
all of the processor power planes rise to their specified values within one second of each other.
The V
CC
power plane must not rise too fast. At least 200
μ
sec (T
R
) must pass from the time that
V
CC
is at 10% of its nominal value until the time that V
CC
is at 90% of its nominal value (see
Figure 3).
Figure 3. Vcc Ramp Rate Requirement
Vcc
Volts
90% Vcc (nominal)
10% Vcc (nominal)
T
R
Time
3.1.2
Test Access Port (TAP) Connection
The TAP interface is an implementation of the IEEE 1149.1 (“JTAG”) standard. Due to the
voltage levels supported by the TAP interface, Intel recommends that the mobile Intel Celeron
processor and the other 1.5-V JTAG specification compliant devices be last in the JTAG chain
after any devices with 3.3-V or 5.0-V JTAG interfaces within the system. A translation buffer
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