參數(shù)資料
型號： RH8053GC033512
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 16/81頁
文件大?。?/td> 598K
代理商： RH8053GC033512
Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Datasheet
Order Number#249563-001
16
Input signals (other than RESET#) may not change while the processor is in the Sleep state or
transitioning into or out of the Sleep state. Input signal changes at these times will cause
unpredictable behavior. Thus, the processor is incapable of snooping or latching any events in the
Sleep state.
While in the Sleep state, the processor can enter its lowest power state, the Deep Sleep state.
Removing the processor’s input clock puts the processor in the Deep Sleep state. PICCLK may be
removed in the Sleep state.
2.2.8
Deep Sleep State
The Deep Sleep state is the lowest power mode the processor can enter while maintaining its
context. The Deep Sleep state is entered by stopping the BCLK input to the processor, while it is
in the Sleep or Quick Start state. For proper operation, the BCLK input should be stopped in the
Low state.
The processor will return to the Sleep or Quick Start state from the Deep Sleep state when the
BCLK input is restarted. Due to the PLL lock latency, there is a delay of up to 30
μ
sec after the
clocks have started before this state transition happens. PICCLK may be removed in the Deep
Sleep state. PICCLK should be designed to turn on when BCLK turns on when transitioning out of
the Deep Sleep state.
The input signal restrictions for the Deep Sleep state are the same as for the Sleep state, except
that RESET# assertion will result in unpredictable behavior.
Table 3. Clock State Characteristics
Clock State
Exit Latency
Snooping
System Uses
Normal
N/A
Yes
Normal program execution
Auto Halt
Approximately 10 bus clocks
Yes
S/W controlled entry idle mode
Stop Grant
10 bus clocks
Yes
H/W controlled entry/exit mobile throttling
Quick Start
Through snoop, to HALT/Grant
Snoop state: immediate
Through STPCLK#, to Normal
state: 8 bus clocks
Yes
H/W controlled entry/exit mobile throttling
HALT/Grant
Snoop
A few bus clocks after the end
of snoop activity
Yes
Supports snooping in the low power states
Sleep
To Stop Grant state 10 bus
clocks
No
H/W controlled entry/exit desktop idle mode
support
Deep Sleep
30
μ
sec
No
H/W controlled entry/exit mobile powered-on
suspend support
NOTE:
See Table 32 for power dissipation in the low-power states.
2.2.9
Operating System Implications of Low-power States
There are a number of architectural features of the mobile Intel Celeron processor that do not
function in the Quick Start or Sleep state as they do in the Stop Grant state. The time-stamp
counter and the performance monitor counters are not guaranteed to count in the Quick Start or
Sleep states. The local APIC timer and performance monitor counter interrupts should be disabled
before entering the Deep Sleep state or the resulting behavior will be unpredictable.
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