參數(shù)資料
型號(hào): RF5C396L
廠商: RICOH COMPANY LTD
元件分類: 總線控制器
英文描述: TRI N PLUG F PLAS 0-48
中文描述: PCMCIA BUS CONTROLLER, PQFP208
封裝: 1.70 MM HEIGHT, PLASTIC, LQFP-208
文件頁(yè)數(shù): 32/93頁(yè)
文件大?。?/td> 449K
代理商: RF5C396L
RF5C296/RF5C396L/RB5C396/RF5C396
28
bit3
: Card Detect 2. This bit specifies reading back of the input CD2# pin signal in the inverted state. This bit
will be set to “1” in the presence of the card in the slot when the IC core is connected to the external pull-
up resistor because the CD2# pin is connected to the GND pin inside the card.
: Card Detect 1. This bit specifies reading back of the input CD1# pin signal in the inverted state. This bit
will be set to “1” in the presence of the card in the slot when the IC core is connected to the external pull-
up resistor because the CD1# pin is connected to the GND pin inside the card.
bit1 to 0 : Battery Voltage Detect 2&1. Bits 1 and 0 can be used to specify reading back of the status of the input
BVD2 and BVD1 pin signals, respectively, when the PC card is the memory card. Bits 1 and 0 can also be
used to specify the battery status as shown in the table below:
bit2
bit0
0
0
1
1
bit1
0
1
0
1
Status
Battery Dead
Battery Dead
Warning
Battery Good
For I/O card, bit0 indicates the current status of the (STSCHG#/RI#) signal from the I/O card when the ring
indicate enable bit in the Interrupt and General Control Register is set to “0”.
Index : 02h
Default value : 0000 0000b
Read & Write
bit7
: Output Enable. When set to “0”, this bit specifies high impedance for slot output signals from the following
pins : CA [25 : 0], CD [15 : 0], CE1#, CE2#, CIORD#, CIOWR#, OE#, REG#, RESET, and WE#. Note that
the pull-down resistor and input slot signal of the DC [15 : 0] pin remain valid.
: Disable Resume RESETDRV. If bit is set to “1” and PWRGOOD=“1”, the restable registers of
RF5C296/RF5C396 will not be reset. If the RESETDRV is a result of a system reset (PWRGOOD= “0”), the
reset able registers of RF5C296/RF5C396 will be reset regardless of the setting bit.
: Auto Power Switch Enable. When this bit is set to “1”, the power control values specified by bits4 to 0
(Power Control Bits) in this register and bit0 in the Mixed Voltage Control Register (Index : 2Fh) are auto-
matically output upon setting of both the CD1# and CD2# pin signals to “0”. Conversely, upon setting of
either the CD1# or CD2# pin signal to “1”, all the the power control values become inactive. When this bit is
set to “0”, the power control values specified by bits4 to 0 (Power Control Bits) in this register and bit0 in
the Mixed Voltage Control Register (Index : 2Fh) are output regardless of whether the CD1# and CD2# pin
signals are set to “0” or “1”.
bit6
bit5
1.3 Power and RESETDRV Control Register
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