
RF5C296/RF5C396L/RB5C396/RF5C396
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A two or three wait state memory access cycle can be implemented by adding the TC1 in the one wait state mem-
ory access cycle of (3). The 16bit memory access cycle is identical to the 16bit I/O cycle in terms of the output tim-
ing for the IOCHRDY pin signal except that the latter is unavailable in zero wait state form.
The RF5C296 and the RF5C396 generate interrupts derived from the following sources :
For I/O Card : Interrupts derived from the IREQ# pin status change :
PC Card status change : CD1# and/or CD2# pin status change
STSCHG# pin status change (when bit7 is set interrupt and
General Control Register (Index : 03h))
5VDET/GPI pin status change
For Memory Card : PC Card status change : CD1# and/or CD2# pin status change
BVD1 and/or BVD2 pin status change
READY#/BUSY# pin status change
5VDET/GPI pin status change
As shown above, interrupt sources fall into two types : interrupts derived from the IREQ# pin and the PC card
status change.
Meanwhile, interrupt output destinations available on the ISA bus are the IRQn pins (n = 3, 4, 5, 7, 9, 10, 11, 12,
14, and 15), the INTR# pin, and the RI_OUT# pin (only for interrupts derived from the CD1# and/or CD2# pin status
change as specified by bit4 (Card Detect Resume Enable Bit) in the Card Detect and General Control Register
(Index : 16h)).
Some of the internal registers provide the following four types of interrupt control :
(1) Control over interrupt sources
(2) Control over interrupt output destinations
(3) Control over interrupt output waveforms
(4) Control over interrupt cancellation
Of the above four types of interrupt control, (1) control over interrupt sources is described in “5. Card Slot Pin
Status Indication and Register Setting” while the other three types are described below.
4. Interrupt Processing