
RF5C296/RF5C396L/RB5C396/RF5C396
59
31h : bit3 to 0
30h : bit7 to 0
33h : bit3 to 0
32h : bit7 to 0
35h : bit5 to 0
34h : bit7 to 0
31h : bit6
31h : bit7
33h : bit7 to 6
35h : bit7
35h : bit6
29h : bit3 to 0
28h : bit7 to 0
2Bh : bit3 to 0
2Ah : bit7 to 0
2Dh : bit5 to 0
2Ch : bit7 to 0
29h : bit6
29h : bit7
2Bh : bit7 to 6
2Dh : bit7
2Dh : bit6
21h : bit3 to 0
20h : bit7 to 0
23h : bit3 to 0
22h : bit7 to 0
25h : bit5 to 0
24h : bit7 to 0
21h : bit6
21h : bit7
23h : bit7 to 6
25h : bit7
25h : bit6
19h : bit3 to 0
18h : bit7 to 0
1Bh : bit3 to 0
1Ah : bit7 to 0
1Dh : bit5 to 0
1Ch : bit7 to 0
19h : bit6
19h : bit7
1Bh : bit7 to 6
1Dh : bit7
1Dh : bit6
11h : bit3 to 0
10h : bit7 to 0
13h : bit3 to 0
12h : bit7 to 0
15h : bit5 to 0
14h : bit7 to 0
11h : bit6
11h : bit7
13h : bit7 to 6
15h : bit7
15h : bit6
Index
Index
Index
Index
Index
Index
Index
Index
Window 0
Window 1 Window 2
Window 3
Window 4
Start
Address
Stop
Address
Offset
Address
Zero Wait
State
Data Size
Wait State
Write
Protect
Reg Active
The settings of the internal registers relating to memory address window setting are shown in the table below.
For details on the individual internal registers, see “INTERNAL REGISTERS”.
These bits can be used to specify the starting address of the applicable memory address window. (A23 to A12)
These bits can be used to specify the ending address of the applicable memory address window. (A23 to A12)
These bits can be used to specify the offset address of the applicable memory address window. (A25 to A12)
These bits can be used to specify zero wait state access when set to “1” in the 8bit mode, giving first priori-
ty to the WAIT# pin signal from the PC card.
These bits can be used to specify 8bit access and 16bit access when set to “0” and “1”, respectively.
These bits can be used to specify memory access cycles, giving first priority to the WAIT# pin signal from
the PC card.
These bits can be used to specify write protection on memory.
These bits can be used to specify access to the attribute memory in the IC card when set to “1”.
bit7
bit6 # of additional cycle
# of SYSCLK per access
0
0
1
1
0
1
0
1
1
2
3
Standard 16bit cycle
(additional cycle is “0”.)
3
4
5
6
Memory Address Window Setting