參數(shù)資料
型號: RD28F6408W30B70
廠商: INTEL CORP
元件分類: 存儲器
英文描述: 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA80
封裝: 14 X 8 MM, 0.80 MM PITCH, STACK, CSP-80
文件頁數(shù): 31/82頁
文件大?。?/td> 749K
代理商: RD28F6408W30B70
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Preliminary
25
The 12 V V
PP
mode enhances programming performance during the short time period typically
found in manufacturing processes; however, it is not intended for extended use. 12 V may be
applied to V
PP
during program and erase operations as specified in
Section 11.2,
Extended
Temperature Operation
on page 35
. V
PP
may be connected to 12 V for a total of t
PPH
hours
maximum. Stressing the device beyond these limits may cause permanent damage.
5.2
Programming Voltage Protection (V
PP
)
In addition to the flexible block locking, holding the V
PP
programming voltage low can provide
absolute hardware write protection of all flash-device blocks. If V
PP
is below V
PPLK
, program or
erase operations will result in an error displayed in the status register bit SR.3 (set to 1).
NOTE:
If the V
CC
supply can sink adequate current, an appropriately valued resistor can be used.
5.3
Enhanced Factory Programming (EFP)
EFP substantially improves device programming performance via a number of enhancements to
the conventional 12-volt word program algorithm. EFP's more efficient WSM algorithm eliminates
the traditional overhead delays of conventional word program mode in both the host programming
system and the flash device. Changes to the flowchart and internal routine were developed because
of today's beat-rate-sensitive manufacturing environments; a balance between programming speed
and cycling performance was struck.
After a single command sequence, host programmer bus cycles write data words followed by status
checks to determine when the next data word is ready to be accepted. This modification essentially
cuts write bus cycles in half. Following each internal program pulse, the WSM automatically
increments the device's address to the next physical location. Now, programming equipment can
sequentially stream program data throughout an entire block without having to setup and present
each new address. In combination, these enhancements reduce much of the host programmer
overhead, enabling more of a data streaming approach to device programming.
Additionally, EFP speeds up programming by performing internal code verification. With this,
PROM programmers can rely on the device to verify that it's been programmed properly. From the
device side, EFP streamlines internal overhead by eliminating the delays previously associated to
switch voltages between programming and verify levels at each memory-word location.
Figure 9. Example of V
PP
Power Supply Configurations
12 V fast programming
Absolute write protection with V
PP
V
PPLK
System supply
(Note 1)
V
CC
V
PP
12 V supply
V
CC
V
PP
Low voltage and 12 V fast programming
System supply
12 V supply
Low-voltage programming
Absolute write protection via logic signal
System supply
V
CC
V
PP
Prot# (logic signal)
Low-voltage programming
System supply
V
CC
V
PP
10K
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