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型號：	RCB005
文件頁數(shù)：	87/1328頁
文件大?。?/td>	9519K
代理商：	RCB005

PRODUCT SPECIFICATION

FSK Decoding with Carrier Detector

The lock detector section of the RC2211A can be used as a

carrier detector option for FSK decoding. The recommended

circuit connection for this application is shown in Figure 3.

The open-collector lock detector output, pin 6, is shorted to

the data output (pin 7). Thus, the data output will be disabled

at “l(fā)ow” state, until there is a carrier within the detection

band of the PLL, and the pin 6 output goes “high” to enable

the data output.

Figure 3. External Connections for

FSK Demodulation with Carrier Detector Capability

The minimum value of the lock detector filter capacitance

is inversely proportional to the capture range,

This is the range of incoming frequencies over which the

loop can acquire lock and is always less than the tracking

range. It is further limited by C

. For most applications,

, the approximate minimum

can be determined by:

16/capture range in Hz

With values of C

that are too small, chatter can be observed

on the lock detector output as an incoming signal frequency

approaches the capture bandwidth. Excessively large values

will slow the response time of the lock detector

Tone Detection

Figure 4 shows the generalized circuit connection for tone

detection. The logic outputs, Q and Q at pins 5 and 6 are

normally at “high” and “l(fā)ow” logic states, respectively.

When a tone is present within the detection band of the PLL,

the logic state at these outputs becomes reversed to the

duration of the input tone. Each logic output can sink 5 mA

of load current.

Data output is "low" when no carrier is present.

Figure 4. Circuit Connection for Tone Detection

Both logic outputs at pins 5 and 6 are open-collector type

stages, and require external pull-up resistors R

shown in Figure 4.

With reference to Figures 1 and 4, the function of the

external circuit components can be explained as follows:

set VCO center frequency, R

sets the detection

bandwidth, C

sets the lowpass-loop filter time constant and

the loop dampening factor, and R

are the respec-

tive pull-up resistors for the Q and Q logic outputs.

Design Instructions

The circuit of Figure 4 can be optimized for any tone-detec-

tion application by the choice of five key circuit components:

. For a given input tone frequency, F

these parameters are calculated as follows:

to be in the range of 15 k

This choice is arbitrary.

to set center frequency, f

to set bandwidth

F (see Design Equa-

tion No. 5): R

F). Note: The total detection

bandwidth covers the frequency range of F

Calculate value of C

for a given loop damping factor:

= 1/2 is optimum for most tone detector

applications, giving C

Increasing C

improves the out-of-band signal rejection,

but increases the PLL capture time.

Calculate value of filter capacitor C

. To avoid chatter

at the logic output, with R

(16/capture range in Hz)

Increasing C

slows the logic output response time.

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